Searched refs:mmUVD_MPC_SET_MUX (Results 1 - 15 of 15) sorted by relevance
| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/ |
| H A D | uvd_4_0_d.h | 57 #define mmUVD_MPC_SET_MUX 0x3D7D macro
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| H A D | uvd_4_2_d.h | 60 #define mmUVD_MPC_SET_MUX 0x3d7d macro
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| H A D | uvd_6_0_d.h | 82 #define mmUVD_MPC_SET_MUX 0x3d7d macro
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| H A D | uvd_5_0_d.h | 66 #define mmUVD_MPC_SET_MUX 0x3d7d macro
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| H A D | uvd_7_0_offset.h | 174 #define mmUVD_MPC_SET_MUX 0x057d macro
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/ |
| H A D | vcn_1_0_offset.h | 356 #define mmUVD_MPC_SET_MUX 0x057d macro
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| H A D | vcn_2_0_0_offset.h | 606 #define mmUVD_MPC_SET_MUX 0x023d macro
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| H A D | vcn_2_5_offset.h | 771 #define mmUVD_MPC_SET_MUX 0x02d2 macro
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | amdgpu_uvd_v5_0.c | 350 WREG32(mmUVD_MPC_SET_MUX, 0x88);
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| H A D | amdgpu_uvd_v4_2.c | 303 WREG32(mmUVD_MPC_SET_MUX, 0x88);
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| H A D | amdgpu_vcn_v1_0.c | 838 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX,
1021 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUX,
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| H A D | amdgpu_vcn_v2_0.c | 811 UVD, 0, mmUVD_MPC_SET_MUX),
934 /* setup mmUVD_MPC_SET_MUX */
935 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX,
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| H A D | amdgpu_vcn_v2_5.c | 819 UVD, 0, mmUVD_MPC_SET_MUX),
961 /* setup mmUVD_MPC_SET_MUX */
962 WREG32_SOC15(UVD, i, mmUVD_MPC_SET_MUX,
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| H A D | amdgpu_uvd_v6_0.c | 766 WREG32(mmUVD_MPC_SET_MUX, 0x88);
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| H A D | amdgpu_uvd_v7_0.c | 1011 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUX, 0x88);
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