Searched refs:mmUVD_MPC_SET_ALU (Results 1 - 12 of 12) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
H A Duvd_4_0_d.h56 #define mmUVD_MPC_SET_ALU 0x3D7E macro
H A Duvd_4_2_d.h61 #define mmUVD_MPC_SET_ALU 0x3d7e macro
H A Duvd_6_0_d.h83 #define mmUVD_MPC_SET_ALU 0x3d7e macro
H A Duvd_5_0_d.h67 #define mmUVD_MPC_SET_ALU 0x3d7e macro
H A Duvd_7_0_offset.h176 #define mmUVD_MPC_SET_ALU 0x057e macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h358 #define mmUVD_MPC_SET_ALU 0x057e macro
H A Dvcn_2_0_0_offset.h608 #define mmUVD_MPC_SET_ALU 0x023e macro
H A Dvcn_2_5_offset.h773 #define mmUVD_MPC_SET_ALU 0x02d3 macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_uvd_v5_0.c349 WREG32(mmUVD_MPC_SET_ALU, 0);
H A Damdgpu_uvd_v4_2.c302 WREG32(mmUVD_MPC_SET_ALU, 0);
H A Damdgpu_uvd_v6_0.c765 WREG32(mmUVD_MPC_SET_ALU, 0);
H A Damdgpu_uvd_v7_0.c1010 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_ALU, 0);

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