Searched refs:mmUVD_LMI_CTRL (Results 1 - 15 of 15) sorted by relevance
| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/ |
| H A D | uvd_4_0_d.h | 49 #define mmUVD_LMI_CTRL 0x3D66 macro
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| H A D | uvd_4_2_d.h | 51 #define mmUVD_LMI_CTRL 0x3d66 macro
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| H A D | uvd_6_0_d.h | 73 #define mmUVD_LMI_CTRL 0x3d66 macro
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| H A D | uvd_5_0_d.h | 57 #define mmUVD_LMI_CTRL 0x3d66 macro
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| H A D | uvd_7_0_offset.h | 158 #define mmUVD_LMI_CTRL 0x0566 macro
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/ |
| H A D | vcn_1_0_offset.h | 338 #define mmUVD_LMI_CTRL 0x0566 macro
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| H A D | vcn_2_0_0_offset.h | 564 #define mmUVD_LMI_CTRL 0x0226 macro
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| H A D | vcn_2_5_offset.h | 961 #define mmUVD_LMI_CTRL 0x04a8 macro
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | amdgpu_vcn_v1_0.c | 808 tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL);
809 WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp |
990 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL,
1044 /* setup mmUVD_LMI_CTRL */
1045 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL,
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| H A D | amdgpu_vcn_v2_0.c | 780 /* setup mmUVD_LMI_CTRL */
790 UVD, 0, mmUVD_LMI_CTRL), tmp, 0, indirect);
906 /* setup mmUVD_LMI_CTRL */
907 tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL);
908 WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp |
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| H A D | amdgpu_vcn_v2_5.c | 788 /* setup mmUVD_LMI_CTRL */
798 UVD, 0, mmUVD_LMI_CTRL), tmp, 0, indirect);
932 /* setup mmUVD_LMI_CTRL */
933 tmp = RREG32_SOC15(UVD, i, mmUVD_LMI_CTRL);
935 WREG32_SOC15(UVD, i, mmUVD_LMI_CTRL, tmp | 0x8|
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| H A D | amdgpu_uvd_v5_0.c | 334 WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |
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| H A D | amdgpu_uvd_v4_2.c | 293 WREG32(mmUVD_LMI_CTRL, 0x203108);
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| H A D | amdgpu_uvd_v7_0.c | 875 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL),
990 WREG32_SOC15(UVD, k, mmUVD_LMI_CTRL,
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| H A D | amdgpu_uvd_v6_0.c | 745 WREG32(mmUVD_LMI_CTRL,
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