Searched refs:mmUVD_GPCOM_VCPU_DATA1 (Results 1 - 16 of 16) sorted by relevance
| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/ |
| H A D | uvd_4_0_d.h | 46 #define mmUVD_GPCOM_VCPU_DATA1 0x3BC5 macro
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| H A D | uvd_4_2_d.h | 34 #define mmUVD_GPCOM_VCPU_DATA1 0x3bc5 macro
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| H A D | uvd_6_0_d.h | 34 #define mmUVD_GPCOM_VCPU_DATA1 0x3bc5 macro
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| H A D | uvd_5_0_d.h | 34 #define mmUVD_GPCOM_VCPU_DATA1 0x3bc5 macro
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| H A D | uvd_7_0_offset.h | 60 #define mmUVD_GPCOM_VCPU_DATA1 0x03c5 macro
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | amdgpu_uvd_v6_0.c | 910 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
917 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
1041 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
1054 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
1069 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
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| H A D | amdgpu_uvd_v5_0.c | 477 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
484 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
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| H A D | amdgpu_uvd_v4_2.c | 460 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
467 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
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| H A D | amdgpu_vcn_v1_0.c | 146 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1);
1475 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1485 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1533 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1567 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
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| H A D | amdgpu_uvd_v7_0.c | 1176 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
1186 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
1351 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
1367 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
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| H A D | amdgpu_uvd.c | 928 case mmUVD_GPCOM_VCPU_DATA1:
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| H A D | amdgpu_vcn_v2_0.c | 155 adev->vcn.inst->external.data1 = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1);
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| H A D | amdgpu_vcn_v2_5.c | 188 adev->vcn.inst[j].external.data1 = SOC15_REG_OFFSET(UVD, j, mmUVD_GPCOM_VCPU_DATA1);
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/ |
| H A D | vcn_1_0_offset.h | 144 #define mmUVD_GPCOM_VCPU_DATA1 0x03c5 macro
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| H A D | vcn_2_0_0_offset.h | 816 #define mmUVD_GPCOM_VCPU_DATA1 0x0585 macro
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| H A D | vcn_2_5_offset.h | 517 #define mmUVD_GPCOM_VCPU_DATA1 0x0091 macro
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