Searched refs:mmUVD_GPCOM_VCPU_CMD (Results 1 - 16 of 16) sorted by relevance
| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/ |
| H A D | uvd_4_0_d.h | 44 #define mmUVD_GPCOM_VCPU_CMD 0x3BC3 macro
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| H A D | uvd_4_2_d.h | 32 #define mmUVD_GPCOM_VCPU_CMD 0x3bc3 macro
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| H A D | uvd_6_0_d.h | 32 #define mmUVD_GPCOM_VCPU_CMD 0x3bc3 macro
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| H A D | uvd_5_0_d.h | 32 #define mmUVD_GPCOM_VCPU_CMD 0x3bc3 macro
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| H A D | uvd_7_0_offset.h | 56 #define mmUVD_GPCOM_VCPU_CMD 0x03c3 macro
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | amdgpu_vcn_v1_0.c | 148 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD);
1433 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1449 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1478 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1488 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1539 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1570 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
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| H A D | amdgpu_uvd_v6_0.c | 912 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
919 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
1043 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
1058 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
1075 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
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| H A D | amdgpu_uvd_v5_0.c | 479 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
486 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
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| H A D | amdgpu_uvd_v4_2.c | 462 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
469 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
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| H A D | amdgpu_uvd_v7_0.c | 1179 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
1189 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
1354 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
1373 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
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| H A D | amdgpu_uvd.c | 931 case mmUVD_GPCOM_VCPU_CMD:
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| H A D | amdgpu_vcn_v2_0.c | 157 adev->vcn.inst->external.cmd = SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD);
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| H A D | amdgpu_vcn_v2_5.c | 190 adev->vcn.inst[j].external.cmd = SOC15_REG_OFFSET(UVD, j, mmUVD_GPCOM_VCPU_CMD);
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/ |
| H A D | vcn_1_0_offset.h | 140 #define mmUVD_GPCOM_VCPU_CMD 0x03c3 macro
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| H A D | vcn_2_0_0_offset.h | 812 #define mmUVD_GPCOM_VCPU_CMD 0x0583 macro
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| H A D | vcn_2_5_offset.h | 513 #define mmUVD_GPCOM_VCPU_CMD 0x008f macro
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