Searched refs:mmUVD_CTX_INDEX (Results 1 - 11 of 11) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
H A Duvd_4_0_d.h42 #define mmUVD_CTX_INDEX 0x3D28 macro
H A Duvd_4_2_d.h42 #define mmUVD_CTX_INDEX 0x3d28 macro
H A Duvd_6_0_d.h64 #define mmUVD_CTX_INDEX 0x3d28 macro
H A Duvd_5_0_d.h48 #define mmUVD_CTX_INDEX 0x3d28 macro
H A Duvd_7_0_offset.h142 #define mmUVD_CTX_INDEX 0x0528 macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h302 #define mmUVD_CTX_INDEX 0x0528 macro
H A Dvcn_2_0_0_offset.h502 #define mmUVD_CTX_INDEX 0x01e8 macro
H A Dvcn_2_5_offset.h605 #define mmUVD_CTX_INDEX 0x00c7 macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_soc15.c180 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
194 address = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_INDEX);
H A Damdgpu_vi.c171 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
182 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
H A Damdgpu_cik.c136 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
147 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));

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