Searched refs:mmUVD_CTX_DATA (Results 1 - 11 of 11) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
H A Duvd_4_0_d.h41 #define mmUVD_CTX_DATA 0x3D29 macro
H A Duvd_4_2_d.h43 #define mmUVD_CTX_DATA 0x3d29 macro
H A Duvd_6_0_d.h65 #define mmUVD_CTX_DATA 0x3d29 macro
H A Duvd_5_0_d.h49 #define mmUVD_CTX_DATA 0x3d29 macro
H A Duvd_7_0_offset.h144 #define mmUVD_CTX_DATA 0x0529 macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h304 #define mmUVD_CTX_DATA 0x0529 macro
H A Dvcn_2_0_0_offset.h504 #define mmUVD_CTX_DATA 0x01e9 macro
H A Dvcn_2_5_offset.h607 #define mmUVD_CTX_DATA 0x00c8 macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_soc15.c181 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
195 data = SOC15_REG_OFFSET(UVD, 0, mmUVD_CTX_DATA);
H A Damdgpu_vi.c172 r = RREG32(mmUVD_CTX_DATA);
183 WREG32(mmUVD_CTX_DATA, (v));
H A Damdgpu_cik.c137 r = RREG32(mmUVD_CTX_DATA);
148 WREG32(mmUVD_CTX_DATA, (v));

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