Searched refs:mmMAILBOX_MSGBUF_TRN_DW0 (Results 1 - 5 of 5) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_mxgpu_vi.c361 reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW0);
364 WREG32_NO_KIQ(mmMAILBOX_MSGBUF_TRN_DW0, reg);
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/nbif/
H A Dnbif_6_1_offset.h1135 #define mmMAILBOX_MSGBUF_TRN_DW0 0x0e56 // duplicate macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/bif/
H A Dbif_5_0_d.h180 #define mmMAILBOX_MSGBUF_TRN_DW0 0x14c8 macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_4_offset.h2916 #define mmMAILBOX_MSGBUF_TRN_DW0 0x0136 macro
H A Dnbio_7_0_offset.h4486 #define mmMAILBOX_MSGBUF_TRN_DW0 0x0136 macro

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