Searched refs:mmIH_RB_WPTR (Results 1 - 14 of 14) sorted by relevance
| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | amdgpu_cik_ih.c | 95 WREG32(mmIH_RB_WPTR, 0);
148 WREG32(mmIH_RB_WPTR, 0);
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| H A D | amdgpu_navi10_ih.c | 76 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0);
154 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0);
224 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR);
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| H A D | amdgpu_iceland_ih.c | 95 WREG32(mmIH_RB_WPTR, 0);
150 WREG32(mmIH_RB_WPTR, 0);
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| H A D | amdgpu_cz_ih.c | 95 WREG32(mmIH_RB_WPTR, 0);
150 WREG32(mmIH_RB_WPTR, 0);
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| H A D | amdgpu_tonga_ih.c | 91 WREG32(mmIH_RB_WPTR, 0);
148 WREG32(mmIH_RB_WPTR, 0);
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| H A D | amdgpu_vega10_ih.c | 125 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0);
275 WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR, 0);
393 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR);
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/oss/ |
| H A D | oss_1_0_d.h | 235 #define mmIH_RB_WPTR 0x0F83 macro
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| H A D | osssys_4_0_1_offset.h | 130 #define mmIH_RB_WPTR 0x0084 macro
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| H A D | osssys_4_0_offset.h | 130 #define mmIH_RB_WPTR 0x0084 macro
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| H A D | osssys_5_0_0_offset.h | 130 #define mmIH_RB_WPTR 0x0084 macro
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| H A D | oss_2_4_d.h | 48 #define mmIH_RB_WPTR 0xe33 macro
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| H A D | oss_2_0_d.h | 48 #define mmIH_RB_WPTR 0xf83 macro
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| H A D | oss_3_0_1_d.h | 48 #define mmIH_RB_WPTR 0xe33 macro
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| H A D | oss_3_0_d.h | 48 #define mmIH_RB_WPTR 0xe33 macro
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