Searched refs:ixSMU_EFUSE_0 (Results 1 - 10 of 10) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/smu/
H A Dsmu_7_0_0_d.h161 #define ixSMU_EFUSE_0 0xc0100000 macro
H A Dsmu_7_1_3_d.h203 #define ixSMU_EFUSE_0 0xc0100000 macro
H A Dsmu_7_1_2_d.h200 #define ixSMU_EFUSE_0 0xc0100000 macro
H A Dsmu_7_1_0_d.h179 #define ixSMU_EFUSE_0 0xc0100000 macro
H A Dsmu_7_0_1_d.h180 #define ixSMU_EFUSE_0 0xc0100000 macro
H A Dsmu_7_1_1_d.h198 #define ixSMU_EFUSE_0 0xc0100000 macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
H A Damdgpu_fiji_smumgr.c1687 ixSMU_EFUSE_0 + (146 * 4));
1689 ixSMU_EFUSE_0 + (148 * 4));
H A Damdgpu_polaris10_smumgr.c331 efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_EFUSE_0 + (49*4));
1533 ixSMU_EFUSE_0 + (67 * 4));
H A Damdgpu_tonga_smumgr.c1603 ixSMU_EFUSE_0 + (146 * 4));
1605 ixSMU_EFUSE_0 + (148 * 4));
H A Damdgpu_vegam_smumgr.c1555 ixSMU_EFUSE_0 + (49 * 4));

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