Searched refs:ixLCAC_MC3_OVR_SEL (Results 1 - 9 of 9) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/smu/
H A Dsmu_6_0_d.h38 #define ixLCAC_MC3_OVR_SEL 0x0126 macro
H A Dsmu_8_0_d.h644 #define ixLCAC_MC3_OVR_SEL 0xd0208158 macro
H A Dsmu_7_0_0_d.h737 #define ixLCAC_MC3_OVR_SEL 0xc0400d58 macro
H A Dsmu_7_1_3_d.h1120 #define ixLCAC_MC3_OVR_SEL 0xc0400158 macro
H A Dsmu_7_1_2_d.h1188 #define ixLCAC_MC3_OVR_SEL 0xc0400158 macro
H A Dsmu_7_1_0_d.h1256 #define ixLCAC_MC3_OVR_SEL 0xc0400d58 macro
H A Dsmu_7_0_1_d.h1227 #define ixLCAC_MC3_OVR_SEL 0xc0400d58 macro
H A Dsmu_7_1_1_d.h1037 #define ixLCAC_MC3_OVR_SEL 0xc0400158 macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_kv_dpm.c555 WREG32_SMC(ixLCAC_MC3_OVR_SEL, 0);

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