1/* $NetBSD: smu_8_0_d.h,v 1.3 2021/12/18 23:45:23 riastradh Exp $ */ 2 3/* 4 * SMU_8_0 Register documentation 5 * 6 * Copyright (C) 2014 Advanced Micro Devices, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included 16 * in all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 22 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 23 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 26#ifndef SMU_8_0_D_H 27#define SMU_8_0_D_H 28 29#define ixTHM_TCON_CSR_CONFIG 0xd82014a4 30#define ixTHM_TCON_CSR_DATA 0xd82014a8 31#define ixTHM_TCON_HTC 0xd8200c64 32#define ixTHM_TCON_CUR_TMP 0xd8200ca4 33#define ixTHM_TCON_THERM_TRIP 0xd8200ce4 34#define ixTHM_GPIO_PROCHOT_CTRL 0xd8200d00 35#define ixTHM_GPIO_THERMTRIP_CTRL 0xd8200d04 36#define ixTHM_THERMAL_INT_ENA 0xd8200d10 37#define ixTHM_THERMAL_INT_CTRL 0xd8200d14 38#define ixTHM_THERMAL_INT_STATUS 0xd8200d18 39#define ixTMON0_RDIL0_DATA 0xd8202000 40#define ixTMON0_RDIL1_DATA 0xd8202004 41#define ixTMON0_RDIL2_DATA 0xd8202008 42#define ixTMON0_RDIL3_DATA 0xd820200c 43#define ixTMON0_RDIL4_DATA 0xd8202010 44#define ixTMON0_RDIL5_DATA 0xd8202014 45#define ixTMON0_RDIL6_DATA 0xd8202018 46#define ixTMON0_RDIL7_DATA 0xd820201c 47#define ixTMON0_RDIL8_DATA 0xd8202020 48#define ixTMON0_RDIL9_DATA 0xd8202024 49#define ixTMON0_RDIL10_DATA 0xd8202028 50#define ixTMON0_RDIL11_DATA 0xd820202c 51#define ixTMON0_RDIL12_DATA 0xd8202030 52#define ixTMON0_RDIL13_DATA 0xd8202034 53#define ixTMON0_RDIL14_DATA 0xd8202038 54#define ixTMON0_RDIL15_DATA 0xd820203c 55#define ixTMON0_RDIR0_DATA 0xd8202040 56#define ixTMON0_RDIR1_DATA 0xd8202044 57#define ixTMON0_RDIR2_DATA 0xd8202048 58#define ixTMON0_RDIR3_DATA 0xd820204c 59#define ixTMON0_RDIR4_DATA 0xd8202050 60#define ixTMON0_RDIR5_DATA 0xd8202054 61#define ixTMON0_RDIR6_DATA 0xd8202058 62#define ixTMON0_RDIR7_DATA 0xd820205c 63#define ixTMON0_RDIR8_DATA 0xd8202060 64#define ixTMON0_RDIR9_DATA 0xd8202064 65#define ixTMON0_RDIR10_DATA 0xd8202068 66#define ixTMON0_RDIR11_DATA 0xd820206c 67#define ixTMON0_RDIR12_DATA 0xd8202070 68#define ixTMON0_RDIR13_DATA 0xd8202074 69#define ixTMON0_RDIR14_DATA 0xd8202078 70#define ixTMON0_RDIR15_DATA 0xd820207c 71#define ixTMON0_INT_DATA 0xd8202080 72#define ixTMON0_RDIL_PRESENT0 0xd8202084 73#define ixTMON0_RDIL_PRESENT1 0xd8202088 74#define ixTMON0_RDIR_PRESENT0 0xd820208c 75#define ixTMON0_RDIR_PRESENT1 0xd8202090 76#define ixTMON0_CONFIG 0xd8202098 77#define ixTMON0_TEMP_CALC_COEFF0 0xd82020a0 78#define ixTMON0_TEMP_CALC_COEFF1 0xd82020a4 79#define ixTMON0_TEMP_CALC_COEFF2 0xd82020a8 80#define ixTMON0_TEMP_CALC_COEFF3 0xd82020ac 81#define ixTMON0_TEMP_CALC_COEFF4 0xd82020b0 82#define ixTMON0_DEBUG0 0xd82020b4 83#define ixTMON0_DEBUG1 0xd82020b8 84#define ixTMON1_RDIL0_DATA 0xd8202100 85#define ixTMON1_RDIL1_DATA 0xd8202104 86#define ixTMON1_RDIL2_DATA 0xd8202108 87#define ixTMON1_RDIL3_DATA 0xd820210c 88#define ixTMON1_RDIL4_DATA 0xd8202110 89#define ixTMON1_RDIL5_DATA 0xd8202114 90#define ixTMON1_RDIL6_DATA 0xd8202118 91#define ixTMON1_RDIL7_DATA 0xd820211c 92#define ixTMON1_RDIL8_DATA 0xd8202120 93#define ixTMON1_RDIL9_DATA 0xd8202124 94#define ixTMON1_RDIL10_DATA 0xd8202128 95#define ixTMON1_RDIL11_DATA 0xd820212c 96#define ixTMON1_RDIL12_DATA 0xd8202130 97#define ixTMON1_RDIL13_DATA 0xd8202134 98#define ixTMON1_RDIL14_DATA 0xd8202138 99#define ixTMON1_RDIL15_DATA 0xd820213c 100#define ixTMON1_RDIR0_DATA 0xd8202140 101#define ixTMON1_RDIR1_DATA 0xd8202144 102#define ixTMON1_RDIR2_DATA 0xd8202148 103#define ixTMON1_RDIR3_DATA 0xd820214c 104#define ixTMON1_RDIR4_DATA 0xd8202150 105#define ixTMON1_RDIR5_DATA 0xd8202154 106#define ixTMON1_RDIR6_DATA 0xd8202158 107#define ixTMON1_RDIR7_DATA 0xd820215c 108#define ixTMON1_RDIR8_DATA 0xd8202160 109#define ixTMON1_RDIR9_DATA 0xd8202164 110#define ixTMON1_RDIR10_DATA 0xd8202168 111#define ixTMON1_RDIR11_DATA 0xd820216c 112#define ixTMON1_RDIR12_DATA 0xd8202170 113#define ixTMON1_RDIR13_DATA 0xd8202174 114#define ixTMON1_RDIR14_DATA 0xd8202178 115#define ixTMON1_RDIR15_DATA 0xd820217c 116#define ixTMON1_INT_DATA 0xd8202180 117#define ixTMON1_RDIL_PRESENT0 0xd8202184 118#define ixTMON1_RDIL_PRESENT1 0xd8202188 119#define ixTMON1_RDIR_PRESENT0 0xd820218c 120#define ixTMON1_RDIR_PRESENT1 0xd8202190 121#define ixTMON1_CONFIG 0xd8202198 122#define ixTMON1_TEMP_CALC_COEFF0 0xd82021a0 123#define ixTMON1_TEMP_CALC_COEFF1 0xd82021a4 124#define ixTMON1_TEMP_CALC_COEFF2 0xd82021a8 125#define ixTMON1_TEMP_CALC_COEFF3 0xd82021ac 126#define ixTMON1_TEMP_CALC_COEFF4 0xd82021b0 127#define ixTMON1_DEBUG0 0xd82021b4 128#define ixTMON1_DEBUG1 0xd82021b8 129#define ixTHM_TMON0_REMOTE_START 0xd8202800 130#define ixTHM_TMON0_REMOTE_END 0xd82028fc 131#define ixTHM_TMON1_REMOTE_START 0xd8202900 132#define ixTHM_TMON1_REMOTE_END 0xd82029fc 133#define ixTHM_TCON_LOCAL0 0xd8202e00 134#define ixTHM_TCON_LOCAL1 0xd8202e04 135#define ixTHM_TCON_LOCAL2 0xd8202e08 136#define ixTHM_TCON_LOCAL3 0xd8202e0c 137#define ixTHM_TCON_LOCAL4 0xd8202e10 138#define ixTHM_TCON_LOCAL5 0xd8202e14 139#define ixTHM_TCON_LOCAL6 0xd8202e18 140#define ixTHM_TCON_LOCAL7 0xd8202e1c 141#define ixTHM_TCON_LOCAL8 0xd8202e20 142#define ixTHM_TCON_LOCAL9 0xd8202e24 143#define ixTHM_TCON_LOCAL10 0xd8202e28 144#define ixTHM_TCON_LOCAL11 0xd8202e2c 145#define ixTHM_TCON_LOCAL12 0xd8202e30 146#define ixTHM_TCON_LOCAL13 0xd8202ef8 147#define ixTHM_TCON_LOCAL14 0xd8202efc 148#define ixTHM_FUSE0 0xd8210000 149#define ixTHM_FUSE1 0xd8210004 150#define ixTHM_FUSE2 0xd8210008 151#define ixTHM_FUSE3 0xd821000c 152#define ixTHM_FUSE4 0xd8210010 153#define ixTHM_FUSE5 0xd8210014 154#define ixTHM_FUSE6 0xd8210018 155#define ixTHM_FUSE7 0xd821001c 156#define ixTHM_FUSE8 0xd8210020 157#define ixTHM_FUSE9 0xd8210024 158#define ixTHM_FUSE10 0xd8210028 159#define ixTHM_FUSE11 0xd821002c 160#define ixTHM_FUSE12 0xd8210030 161#define mmMP0PUB_IND_INDEX 0x180 162#define mmMP_SMUIF0_MP0PUB_IND_INDEX 0x180 163#define mmMP_SMUIF1_MP0PUB_IND_INDEX 0x182 164#define mmMP_SMUIF2_MP0PUB_IND_INDEX 0x184 165#define mmMP_SMUIF3_MP0PUB_IND_INDEX 0x186 166#define mmMP_SMUIF4_MP0PUB_IND_INDEX 0x188 167#define mmMP_SMUIF5_MP0PUB_IND_INDEX 0x18a 168#define mmMP_SMUIF6_MP0PUB_IND_INDEX 0x18c 169#define mmMP_SMUIF7_MP0PUB_IND_INDEX 0x18e 170#define mmMP_SMUIF8_MP0PUB_IND_INDEX 0x190 171#define mmMP_SMUIF9_MP0PUB_IND_INDEX 0x192 172#define mmMP_SMUIF10_MP0PUB_IND_INDEX 0x194 173#define mmMP_SMUIF11_MP0PUB_IND_INDEX 0x196 174#define mmMP_SMUIF12_MP0PUB_IND_INDEX 0x198 175#define mmMP_SMUIF13_MP0PUB_IND_INDEX 0x19a 176#define mmMP_SMUIF14_MP0PUB_IND_INDEX 0x19c 177#define mmMP_SMUIF15_MP0PUB_IND_INDEX 0x19e 178#define mmMP0PUB_IND_DATA 0x181 179#define mmMP_SMUIF0_MP0PUB_IND_DATA 0x181 180#define mmMP_SMUIF1_MP0PUB_IND_DATA 0x183 181#define mmMP_SMUIF2_MP0PUB_IND_DATA 0x185 182#define mmMP_SMUIF3_MP0PUB_IND_DATA 0x187 183#define mmMP_SMUIF4_MP0PUB_IND_DATA 0x189 184#define mmMP_SMUIF5_MP0PUB_IND_DATA 0x18b 185#define mmMP_SMUIF6_MP0PUB_IND_DATA 0x18d 186#define mmMP_SMUIF7_MP0PUB_IND_DATA 0x18f 187#define mmMP_SMUIF8_MP0PUB_IND_DATA 0x191 188#define mmMP_SMUIF9_MP0PUB_IND_DATA 0x193 189#define mmMP_SMUIF10_MP0PUB_IND_DATA 0x195 190#define mmMP_SMUIF11_MP0PUB_IND_DATA 0x197 191#define mmMP_SMUIF12_MP0PUB_IND_DATA 0x199 192#define mmMP_SMUIF13_MP0PUB_IND_DATA 0x19b 193#define mmMP_SMUIF14_MP0PUB_IND_DATA 0x19d 194#define mmMP_SMUIF15_MP0PUB_IND_DATA 0x19f 195#define mmMP0PUB_IND_INDEX_0 0x180 196#define mmMP0PUB_IND_DATA_0 0x181 197#define mmMP0PUB_IND_INDEX_1 0x182 198#define mmMP0PUB_IND_DATA_1 0x183 199#define mmMP0PUB_IND_INDEX_2 0x184 200#define mmMP0PUB_IND_DATA_2 0x185 201#define mmMP0PUB_IND_INDEX_3 0x186 202#define mmMP0PUB_IND_DATA_3 0x187 203#define mmMP0PUB_IND_INDEX_4 0x188 204#define mmMP0PUB_IND_DATA_4 0x189 205#define mmMP0PUB_IND_INDEX_5 0x18a 206#define mmMP0PUB_IND_DATA_5 0x18b 207#define mmMP0PUB_IND_INDEX_6 0x18c 208#define mmMP0PUB_IND_DATA_6 0x18d 209#define mmMP0PUB_IND_INDEX_7 0x18e 210#define mmMP0PUB_IND_DATA_7 0x18f 211#define mmMP0PUB_IND_INDEX_8 0x190 212#define mmMP0PUB_IND_DATA_8 0x191 213#define mmMP0PUB_IND_INDEX_9 0x192 214#define mmMP0PUB_IND_DATA_9 0x193 215#define mmMP0PUB_IND_INDEX_10 0x194 216#define mmMP0PUB_IND_DATA_10 0x195 217#define mmMP0PUB_IND_INDEX_11 0x196 218#define mmMP0PUB_IND_DATA_11 0x197 219#define mmMP0PUB_IND_INDEX_12 0x198 220#define mmMP0PUB_IND_DATA_12 0x199 221#define mmMP0PUB_IND_INDEX_13 0x19a 222#define mmMP0PUB_IND_DATA_13 0x19b 223#define mmMP0PUB_IND_INDEX_14 0x19c 224#define mmMP0PUB_IND_DATA_14 0x19d 225#define mmMP0PUB_IND_INDEX_15 0x19e 226#define mmMP0PUB_IND_DATA_15 0x19f 227#define mmMP0_IND_ACCESS_CNTL 0x1a0 228#define mmMP0_MSP_MESSAGE_0 0x1a1 229#define mmMP0_MSP_MESSAGE_1 0x1a2 230#define mmMP0_MSP_MESSAGE_2 0x1a3 231#define mmMP0_MSP_MESSAGE_3 0x1a4 232#define mmMP0_MSP_MESSAGE_4 0x1a5 233#define mmMP0_MSP_MESSAGE_5 0x1a6 234#define mmMP0_MSP_MESSAGE_6 0x1a7 235#define mmMP0_MSP_MESSAGE_7 0x1a8 236#define mmSAM_IH_EXT_ERR_INTR 0x1a9 237#define mmSAM_IH_EXT_ERR_INTR_STATUS 0x1aa 238#define mmMP0_DISP_TIMER0_CTRL0 0x1ab 239#define mmMP0_DISP_TIMER0_CTRL1 0x1ac 240#define mmMP0_DISP_TIMER0_CMP_AUTOINC 0x1ad 241#define mmMP0_DISP_TIMER0_INTEN 0x1ae 242#define mmMP0_DISP_TIMER0_OCMP_0_0 0x1af 243#define mmMP0_DISP_TIMER0_OCMP_0_1 0x1b0 244#define mmMP0_DISP_TIMER0_CNT 0x1b1 245#define mmMP0_DISP_TIMER1_CTRL0 0x1b2 246#define mmMP0_DISP_TIMER1_CTRL1 0x1b3 247#define mmMP0_DISP_TIMER1_CMP_AUTOINC 0x1b4 248#define mmMP0_DISP_TIMER1_INTEN 0x1b5 249#define mmMP0_DISP_TIMER1_OCMP_0_0 0x1b6 250#define mmMP0_DISP_TIMER1_OCMP_0_1 0x1b7 251#define mmMP0_DISP_TIMER1_CNT 0x1b8 252#define mmSMU_MP1_SRBM2P_MSG_0 0x1c0 253#define mmSMU_MP1_SRBM2P_MSG_1 0x1c1 254#define mmSMU_MP1_SRBM2P_MSG_2 0x1c2 255#define mmSMU_MP1_SRBM2P_MSG_3 0x1c3 256#define mmSMU_MP1_SRBM2P_MSG_4 0x1c4 257#define mmSMU_MP1_SRBM2P_MSG_5 0x1c5 258#define mmSMU_MP1_SRBM2P_MSG_6 0x1c6 259#define mmSMU_MP1_SRBM2P_MSG_7 0x1c7 260#define mmSMU_MP1_SRBM2P_MSG_8 0x1c8 261#define mmSMU_MP1_SRBM2P_MSG_9 0x1c9 262#define mmSMU_MP1_SRBM2P_MSG_10 0x1ca 263#define mmSMU_MP1_SRBM2P_MSG_11 0x1cb 264#define mmSMU_MP1_SRBM2P_MSG_12 0x1cc 265#define mmSMU_MP1_SRBM2P_MSG_13 0x1cd 266#define mmSMU_MP1_SRBM2P_MSG_14 0x1ce 267#define mmSMU_MP1_SRBM2P_MSG_15 0x1cf 268#define mmSMU_MP1_SRBM2P_RESP_0 0x1d0 269#define mmSMU_MP1_SRBM2P_RESP_1 0x1d1 270#define mmSMU_MP1_SRBM2P_RESP_2 0x1d2 271#define mmSMU_MP1_SRBM2P_RESP_3 0x1d3 272#define mmSMU_MP1_SRBM2P_RESP_4 0x1d4 273#define mmSMU_MP1_SRBM2P_RESP_5 0x1d5 274#define mmSMU_MP1_SRBM2P_RESP_6 0x1d6 275#define mmSMU_MP1_SRBM2P_RESP_7 0x1d7 276#define mmSMU_MP1_SRBM2P_RESP_8 0x1d8 277#define mmSMU_MP1_SRBM2P_RESP_9 0x1d9 278#define mmSMU_MP1_SRBM2P_RESP_10 0x1da 279#define mmSMU_MP1_SRBM2P_RESP_11 0x1db 280#define mmSMU_MP1_SRBM2P_RESP_12 0x1dc 281#define mmSMU_MP1_SRBM2P_RESP_13 0x1dd 282#define mmSMU_MP1_SRBM2P_RESP_14 0x1de 283#define mmSMU_MP1_SRBM2P_RESP_15 0x1df 284#define mmSMU_MP1_SRBM2P_ARG_0 0x1e0 285#define mmSMU_MP1_SRBM2P_ARG_1 0x1e1 286#define mmSMU_MP1_SRBM2P_ARG_2 0x1e2 287#define mmSMU_MP1_SRBM2P_ARG_3 0x1e3 288#define mmSMU_MP1_SRBM2P_ARG_4 0x1e4 289#define mmSMU_MP1_SRBM2P_ARG_5 0x1e5 290#define mmSMU_MP1_SRBM2P_ARG_6 0x1e6 291#define mmSMU_MP1_SRBM2P_ARG_7 0x1e7 292#define mmSMU_MP1_SRBM2P_ARG_8 0x1e8 293#define mmSMU_MP1_SRBM2P_ARG_9 0x1e9 294#define mmSMU_MP1_SRBM2P_ARG_10 0x1ea 295#define mmSMU_MP1_SRBM2P_ARG_11 0x1eb 296#define mmSMU_MP1_SRBM2P_ARG_12 0x1ec 297#define mmSMU_MP1_SRBM2P_ARG_13 0x1ed 298#define mmSMU_MP1_SRBM2P_ARG_14 0x1ee 299#define mmSMU_MP1_SRBM2P_ARG_15 0x1ef 300#define mmSMU_MP1_ACP2MP_RESP 0x1f0 301#define mmSMU_MP1_DC2MP_RESP 0x1f1 302#define mmSMU_MP1_UVD2MP_RESP 0x1f2 303#define mmSMU_MP1_VCE2MP_RESP 0x1f3 304#define mmSMU_MP1_RLC2MP_RESP 0x1f4 305#define mmMP_FPS_CNT 0x1f5 306#define mmSMU_DISP0_TIMER_INT_CONTROL 0x1f6 307#define mmSMU_DISP1_TIMER_INT_CONTROL 0x1f7 308#define mmSMU_SRBM_CONFIG 0x1f8 309#define ixMP_FPS_CNT_XBAR 0xcf200800 310#define ixMP_SRBM_CONFIG_XBAR 0xcf200804 311#define ixMP_SRBM_CONTROL 0xcf200c00 312#define ixMP_SRBM_ACCVIO_LOG 0xcf200c04 313#define ixMP_SRBM_ACCVIO_ADDR 0xcf200c08 314#define ixMP_CRBBM_CONTROL 0xcf200c0c 315#define ixMP_CRBBM_ACCVIO_LOG 0xcf200c10 316#define ixMP_CRBBM_ACCVIO_ADDR 0xcf200c14 317#define ixMP_DRAM_CNTL_WRREQ_CNTL 0xcf200000 318#define ixMP_DRAM_CNTL_WRREQ_CNTL_1 0xcf200004 319#define ixMP_DRAM_CNTL_WRREQ_LOW_ADDR 0xcf200008 320#define ixMP_DRAM_CNTL_WRREQ_HIGH_ADDR 0xcf20000c 321#define ixMP_DRAM_CNTL_WRREQ_MASK 0xcf200010 322#define ixMP_DRAM_CNTL_WRREQ_DATA_0 0xcf200014 323#define ixMP_DRAM_CNTL_WRREQ_DATA_1 0xcf200018 324#define ixMP_DRAM_CNTL_WRREQ_DATA_2 0xcf20001c 325#define ixMP_DRAM_CNTL_WRREQ_DATA_3 0xcf200020 326#define ixMP_DRAM_CNTL_WRREQ_DATA_4 0xcf200024 327#define ixMP_DRAM_CNTL_WRREQ_DATA_5 0xcf200028 328#define ixMP_DRAM_CNTL_WRREQ_DATA_6 0xcf20002c 329#define ixMP_DRAM_CNTL_WRREQ_DATA_7 0xcf200030 330#define ixMP_DRAM_CNTL_WRREQ_STATUS 0xcf200038 331#define ixMP_DRAM_CNTL_WRRET_STATUS_0 0xcf20003c 332#define ixMP_DRAM_CNTL_RDREQ_ADDR 0xcf200040 333#define ixMP_DRAM_CNTL_RDREQ_CNTL 0xcf200044 334#define ixMP_DRAM_CNTL_RDREQ_CNTL_1 0xcf200048 335#define ixMP_DRAM_CNTL_RDRET_VALID 0xcf20004c 336#define ixMP_DRAM_CNTL_RDRET_NACK 0xcf200050 337#define ixMP_DRAM_CNTL_RDRET_DATA_0 0xcf200054 338#define ixMP_DRAM_CNTL_RDRET_DATA_1 0xcf200058 339#define ixMP_DRAM_CNTL_RDRET_DATA_2 0xcf20005c 340#define ixMP_DRAM_CNTL_RDRET_DATA_3 0xcf200060 341#define ixMP_DRAM_CNTL_RDRET_DATA_4 0xcf200064 342#define ixMP_DRAM_CNTL_RDRET_DATA_5 0xcf200068 343#define ixMP_DRAM_CNTL_RDRET_DATA_6 0xcf20006c 344#define ixMP_DRAM_CNTL_RDRET_DATA_7 0xcf200070 345#define ixMP_DRAM_CNTL_RDRET_DATA_8 0xcf200074 346#define ixMP_DRAM_CNTL_RDRET_DATA_9 0xcf200078 347#define ixMP_DRAM_CNTL_RDRET_DATA_10 0xcf20007c 348#define ixMP_DRAM_CNTL_RDRET_DATA_11 0xcf200080 349#define ixMP_DRAM_CNTL_RDRET_DATA_12 0xcf200084 350#define ixMP_DRAM_CNTL_RDRET_DATA_13 0xcf200088 351#define ixMP_DRAM_CNTL_RDRET_DATA_14 0xcf20008c 352#define ixMP_DRAM_CNTL_RDRET_DATA_15 0xcf200090 353#define ixMP_DRAM_CNTL_RDRET_DATA_16 0xcf200094 354#define ixMP_DRAM_CNTL_RDRET_DATA_17 0xcf200098 355#define ixMP_DRAM_CNTL_RDRET_DATA_18 0xcf20009c 356#define ixMP_DRAM_CNTL_RDRET_DATA_19 0xcf2000a0 357#define ixMP_DRAM_CNTL_RDRET_DATA_20 0xcf2000a4 358#define ixMP_DRAM_CNTL_RDRET_DATA_21 0xcf2000a8 359#define ixMP_DRAM_CNTL_RDRET_DATA_22 0xcf2000ac 360#define ixMP_DRAM_CNTL_RDRET_DATA_23 0xcf2000b0 361#define ixMP_DRAM_CNTL_RDRET_DATA_24 0xcf2000b4 362#define ixMP_DRAM_CNTL_RDRET_DATA_25 0xcf2000b8 363#define ixMP_DRAM_CNTL_RDRET_DATA_26 0xcf2000bc 364#define ixMP_DRAM_CNTL_RDRET_DATA_27 0xcf2000c0 365#define ixMP_DRAM_CNTL_RDRET_DATA_28 0xcf2000c4 366#define ixMP_DRAM_CNTL_RDRET_DATA_29 0xcf2000c8 367#define ixMP_DRAM_CNTL_RDRET_DATA_30 0xcf2000cc 368#define ixMP_DRAM_CNTL_RDRET_DATA_31 0xcf2000d0 369#define ixMP_DRAM_CNTL_RDRET_DATA_32 0xcf2000d4 370#define ixMP_DRAM_CNTL_RDRET_DATA_33 0xcf2000d8 371#define ixMP_DRAM_CNTL_RDRET_DATA_34 0xcf2000dc 372#define ixMP_DRAM_CNTL_RDRET_DATA_35 0xcf2000e0 373#define ixMP_DRAM_CNTL_RDRET_DATA_36 0xcf2000e4 374#define ixMP_DRAM_CNTL_RDRET_DATA_37 0xcf2000e8 375#define ixMP_DRAM_CNTL_RDRET_DATA_38 0xcf2000ec 376#define ixMP_DRAM_CNTL_RDRET_DATA_39 0xcf2000f0 377#define ixMP_DRAM_CNTL_RDRET_DATA_40 0xcf2000f4 378#define ixMP_DRAM_CNTL_RDRET_DATA_41 0xcf2000f8 379#define ixMP_DRAM_CNTL_RDRET_DATA_42 0xcf2000fc 380#define ixMP_DRAM_CNTL_RDRET_DATA_43 0xcf200100 381#define ixMP_DRAM_CNTL_RDRET_DATA_44 0xcf200104 382#define ixMP_DRAM_CNTL_RDRET_DATA_45 0xcf200108 383#define ixMP_DRAM_CNTL_RDRET_DATA_46 0xcf20010c 384#define ixMP_DRAM_CNTL_RDRET_DATA_47 0xcf200110 385#define ixMP_DRAM_CNTL_RDRET_DATA_48 0xcf200114 386#define ixMP_DRAM_CNTL_RDRET_DATA_49 0xcf200118 387#define ixMP_DRAM_CNTL_RDRET_DATA_50 0xcf20011c 388#define ixMP_DRAM_CNTL_RDRET_DATA_51 0xcf200120 389#define ixMP_DRAM_CNTL_RDRET_DATA_52 0xcf200124 390#define ixMP_DRAM_CNTL_RDRET_DATA_53 0xcf200128 391#define ixMP_DRAM_CNTL_RDRET_DATA_54 0xcf20012c 392#define ixMP_DRAM_CNTL_RDRET_DATA_55 0xcf200130 393#define ixMP_DRAM_CNTL_RDRET_DATA_56 0xcf200134 394#define ixMP_DRAM_CNTL_RDRET_DATA_57 0xcf200138 395#define ixMP_DRAM_CNTL_RDRET_DATA_58 0xcf20013c 396#define ixMP_DRAM_CNTL_RDRET_DATA_59 0xcf200140 397#define ixMP_DRAM_CNTL_RDRET_DATA_60 0xcf200144 398#define ixMP_DRAM_CNTL_RDRET_DATA_61 0xcf200148 399#define ixMP_DRAM_CNTL_RDRET_DATA_62 0xcf20014c 400#define ixMP_DRAM_CNTL_RDRET_DATA_63 0xcf200150 401#define ixMP_IOC_CTRL 0xcf100000 402#define ixMP_IOC_RDDATA 0xcf100004 403#define ixMP_IOC_PHASE1 0xcf100008 404#define ixMP_IOC_PHASE2 0xcf10000c 405#define ixMP_IOC_PHASE3 0xcf100010 406#define ixMP_IOC_READ_0 0xcf100024 407#define ixMP_IOC_READ_1 0xcf100028 408#define ixMP_IOC_READ_2 0xcf10002c 409#define ixMP_IOC_READ_3 0xcf100030 410#define ixMP_IOC_READ_4 0xcf100034 411#define ixMP_IOC_READ_5 0xcf100038 412#define ixMP_IOC_READ_6 0xcf10003c 413#define ixMP_IOC_READ_7 0xcf100040 414#define ixMP_IOC_READ_8 0xcf100044 415#define ixMP_IOC_READ_9 0xcf100048 416#define ixMP_IOC_READ_10 0xcf10004c 417#define ixMP_IOC_READ_11 0xcf100050 418#define ixMP_IOC_READ_12 0xcf100054 419#define ixMP_IOC_READ_13 0xcf100058 420#define ixMP_IOC_READ_14 0xcf10005c 421#define ixMP_IOC_READ_15 0xcf100060 422#define ixMP_IOC_WRITE_0 0xcf100064 423#define ixMP_IOC_WRITE_1 0xcf100068 424#define ixMP_IOC_WRITE_2 0xcf10006c 425#define ixMP_IOC_WRITE_3 0xcf100070 426#define ixMP_IOC_WRITE_4 0xcf100074 427#define ixMP_IOC_WRITE_5 0xcf100078 428#define ixMP_IOC_WRITE_6 0xcf10007c 429#define ixMP_IOC_WRITE_7 0xcf100080 430#define ixMP_IOC_WRITE_8 0xcf100084 431#define ixMP_IOC_WRITE_9 0xcf100088 432#define ixMP_IOC_WRITE_10 0xcf10008c 433#define ixMP_IOC_WRITE_11 0xcf100090 434#define ixMP_IOC_WRITE_12 0xcf100094 435#define ixMP_IOC_WRITE_13 0xcf100098 436#define ixMP_IOC_WRITE_14 0xcf10009c 437#define ixMP_IOC_WRITE_15 0xcf1000a0 438#define ixMP_INTERRUPT_CONTROL 0xcf200400 439#define ixMP0_SW_INT 0xcf200404 440#define ixMP0_SW_INT_CTXID 0xcf200408 441#define ixMP1_SW_INT 0xcf20040c 442#define ixMP1_SW_INT_CTXID 0xcf200410 443#define ixDISP_TIMER_ID 0xcf200414 444#define mmPWRHW_SMC_IND_INDEX 0x180 445#define mmPWRHW0_PWRHW_SMC_IND_INDEX 0x180 446#define mmPWRHW1_PWRHW_SMC_IND_INDEX 0x182 447#define mmPWRHW2_PWRHW_SMC_IND_INDEX 0x184 448#define mmPWRHW3_PWRHW_SMC_IND_INDEX 0x186 449#define mmPWRHW_SMC_IND_DATA 0x181 450#define mmPWRHW0_PWRHW_SMC_IND_DATA 0x181 451#define mmPWRHW1_PWRHW_SMC_IND_DATA 0x183 452#define mmPWRHW2_PWRHW_SMC_IND_DATA 0x185 453#define mmPWRHW3_PWRHW_SMC_IND_DATA 0x187 454#define ixCURRENT_STATE_CPU0 0xd0210000 455#define ixCURRENT_STATE_CPU1 0xd0210010 456#define ixCPU_REDUN_DONE0 0xd0210004 457#define ixCPU_REDUN_DONE1 0xd0210014 458#define ixCURRENT_VID_CPU0 0xd0210008 459#define ixCURRENT_VID_CPU1 0xd0210018 460#define ixUNBPM_PWRMGT_ACK 0xd0211000 461#define ixCURRENT_FREQ_STATE_NB 0xd0211004 462#define ixCURRENT_PSTATE_NB 0xd0211008 463#define ixUNBPM_MSG_INT_CONFIG 0xd021100c 464#define ixUNBPM_NBPWRMGT_CMD 0xd0211010 465#define ixUNBPM_NBPWRMGT_FSM_CFG 0xd0211014 466#define ixDDR0_FUSE_SSB_XFER 0xd0211018 467#define ixDDR0_FUSE_SSB_XFER_CFG 0xd021101c 468#define ixDDR1_FUSE_SSB_XFER 0xd0211020 469#define ixDDR1_FUSE_SSB_XFER_CFG 0xd0211024 470#define ixUNBPM_FUSES_VAL_PWROK 0xd0211028 471#define ixSYNFIFO_CLK_RATIO 0xd021102c 472#define ixMISC_SMU_PWRMGT_CFG0 0xd0211030 473#define ixMISC_GNB_PWRMGT_CFG1 0xd0211034 474#define ixMISC_SMU_PWRMGT_CFG1 0xd0211038 475#define ixMISC_GNB_PWRMGT_DATA 0xd021103c 476#define ixGN_GNB_SLOW 0xd0211040 477#define ixGN_FORCE_NBPS1 0xd0211044 478#define ixMISC_SMU_PWRMGT_DATA 0xd0211048 479#define ixNB_COF 0xd021104c 480#define ixUNBPM_CK_IRESET 0xd0211050 481#define ixCURRENT_VID_NB 0xd0211054 482#define ixSPR_FUSE_PSTATEPWR1 0xd0211058 483#define ixSPR_FUSE_PSTATEPWR2 0xd021105c 484#define ixSPR_FUSE_PSTATEPWR3 0xd0211060 485#define ixSPR_FUSE_THERMAL_SCRATCH 0xd0211064 486#define ixSPR_PRODUCT_INFO0 0xd0211068 487#define ixSPR_SERIALNUM_REG1 0xd021106c 488#define ixSPR_SERIALNUM_REG2 0xd0211070 489#define ixSPR_PRODUCT_INFO1 0xd0211074 490#define ixSPR_EXT_PRODUCT_INFO 0xd021107c 491#define ixSPR_MSIDFUSE 0xd0211080 492#define ixSPR_LINK_PRODUCT_INFO 0xd0211084 493#define ixSPR_BRAND_NAME_ADDR 0xd0211088 494#define ixSPR_BRAND_NAME_DATA 0xd021108c 495#define ixSPR_COMBO_PHY_PRODUCT_INFO 0xd0211090 496#define ixMISC_GNB_PWRMGT_CFG0 0xd0211094 497#define ixUNBPM_EXIT_TO_PSTATE 0xd0211098 498#define ixUNBPM_WARM_RESET_HS_STATUS 0xd021109c 499#define ixUNBPM_VOLTAGE_CNTL 0xd02110a0 500#define ixUNBPM_VOLTAGE_STATUS 0xd02110a4 501#define ixNUM_BOOST_STATES 0xd02110a8 502#define ixWARM_RESET_NB_CONTROL 0xd02110ac 503#define ixONION_NO_STREAMS_PEND 0xd02110b0 504#define ixSPR_PROGRAMMABLE_CTRL 0xd02110b4 505#define ixPHN_FUSERX_MISC_FUSES 0xd02110b8 506#define ixUNBPM_PWRCTRL_MISC 0xd02110bc 507#define ixCSTATE_ACTIVE_SAMPLER 0xd02110c0 508#define ixUNBPM_DEBUG_CONFIG_STATUS 0xd02110c4 509#define ixUNBPM_AXIMST_LAST_CMD 0xd02110c8 510#define ixUNB_IF_INTRGEN_LAST_SENT 0xd02110cc 511#define ixUNBPM_DEBUG_BUS_CNTL 0xd02110d0 512#define ixUNBPM_PWRMGT_REQ_DBG_STATUS 0xd02110d4 513#define ixUNBPM_VIDCHG_REQ_DBG_STATUS 0xd02110d8 514#define ixUNBPM_SCRATCH_0 0xd021e000 515#define ixUNBPM_SCRATCH_1 0xd021e004 516#define ixPOWERON_CPU_0 0xd0220000 517#define ixPOWERREADY_CPU_0 0xd0220004 518#define ixPGRUNFEEDBACK_CPU_0 0xd0220008 519#define ixRCC3ON_CPU_0 0xd022000c 520#define ixRCC3EXITDONE_CPU_0 0xd0220010 521#define ixCORE_FUNC_LATE_SSB_XFER_0 0xd0220014 522#define ixCORE_FUNC_LATE_SSB_XFER_CFG_0 0xd0220018 523#define ixCORE_REDUN_SSB_XFER_0 0xd022001c 524#define ixCORE_REDUN_SSB_XFER_CFG_0 0xd0220020 525#define ixCORE_APM_SSB_XFER_0 0xd0220024 526#define ixCORE_APM_SSB_XFER_CFG_0 0xd0220028 527#define ixCOREPM_PWRCTRL_MISC_0 0xd022002c 528#define ixLDOIVRON_CPU_0 0xd0220030 529#define ixLDOIVREXITDONE_CPU_0 0xd0220034 530#define ixRCC3_TARGETPSMREF_CPU_0 0xd0220038 531#define ixIVR_TARGETPSMREF_CPU_0 0xd022003c 532#define ixCK_JTCOOLRESET_LATCHED_CPU_0 0xd0220044 533#define ixCK_DISABLECORE_CPU_0 0xd0220048 534#define ixCOREPM_ID_0 0xd022004c 535#define ixCOREPM_SCRATCH_0 0xd0220050 536#define ixRCC3_WAKEMIN_CPU_0 0xd0220054 537#define ixSPMI_CONFIG0_0 0xd0221000 538#define ixSPMI_CONFIG1_0 0xd0221004 539#define ixSPMI_FSM_READ_TRIGGER_0 0xd0221008 540#define ixSPMI_FSM_WRITE_TRIGGER_0 0xd022100c 541#define ixSPMI_FSM_RESET_TRIGGER_0 0xd0221010 542#define ixSPMI_FSM_BUSY_0 0xd0221014 543#define ixSPMI_PATH_0 0xd0221018 544#define ixSPMI_C6_STATE_0 0xd022101c 545#define ixSPMI_JTAG_OVER_0 0xd0221020 546#define ixSPMI_SRAM_ADDRESS_0 0xd0221024 547#define ixSPMI_SRAM_DATA_0 0xd0221028 548#define ixSPMI_RESET_0 0xd022102c 549#define ixSPMI_FORCE_CLOCK_GATERS_0 0xd0221030 550#define ixSPMI_SPARE_0 0xd0221034 551#define ixSPMI_SPARE_EX_0 0xd0221038 552#define ixSPMI_SRAM_CLK_GATER_0 0xd022103c 553#define ixPOWERON_CPU_1 0xd0230000 554#define ixPOWERREADY_CPU_1 0xd0230004 555#define ixPGRUNFEEDBACK_CPU_1 0xd0230008 556#define ixRCC3ON_CPU_1 0xd023000c 557#define ixRCC3EXITDONE_CPU_1 0xd0230010 558#define ixCORE_FUNC_LATE_SSB_XFER_1 0xd0230014 559#define ixCORE_FUNC_LATE_SSB_XFER_CFG_1 0xd0230018 560#define ixCORE_REDUN_SSB_XFER_1 0xd023001c 561#define ixCORE_REDUN_SSB_XFER_CFG_1 0xd0230020 562#define ixCORE_APM_SSB_XFER_1 0xd0230024 563#define ixCORE_APM_SSB_XFER_CFG_1 0xd0230028 564#define ixCOREPM_PWRCTRL_MISC_1 0xd023002c 565#define ixLDOIVRON_CPU_1 0xd0230030 566#define ixLDOIVREXITDONE_CPU_1 0xd0230034 567#define ixRCC3_TARGETPSMREF_CPU_1 0xd0230038 568#define ixIVR_TARGETPSMREF_CPU_1 0xd023003c 569#define ixCK_JTCOOLRESET_LATCHED_CPU_1 0xd0230044 570#define ixCK_DISABLECORE_CPU_1 0xd0230048 571#define ixCOREPM_ID_1 0xd023004c 572#define ixCOREPM_SCRATCH_1 0xd0230050 573#define ixRCC3_WAKEMIN_CPU_1 0xd0230054 574#define ixSPMI_CONFIG0_1 0xd0231000 575#define ixSPMI_CONFIG1_1 0xd0231004 576#define ixSPMI_FSM_READ_TRIGGER_1 0xd0231008 577#define ixSPMI_FSM_WRITE_TRIGGER_1 0xd023100c 578#define ixSPMI_FSM_RESET_TRIGGER_1 0xd0231010 579#define ixSPMI_FSM_BUSY_1 0xd0231014 580#define ixSPMI_PATH_1 0xd0231018 581#define ixSPMI_C6_STATE_1 0xd023101c 582#define ixSPMI_JTAG_OVER_1 0xd0231020 583#define ixSPMI_SRAM_ADDRESS_1 0xd0231024 584#define ixSPMI_SRAM_DATA_1 0xd0231028 585#define ixSPMI_RESET_1 0xd023102c 586#define ixSPMI_FORCE_CLOCK_GATERS_1 0xd0231030 587#define ixSPMI_SPARE_1 0xd0231034 588#define ixSPMI_SPARE_EX_1 0xd0231038 589#define ixSPMI_SRAM_CLK_GATER_1 0xd023103c 590#define ixGENERAL_PWRMGT 0xd0200000 591#define ixCNB_PWRMGT_CNTL 0xd0200004 592#define ixSCLK_PWRMGT_CNTL 0xd0200008 593#define ixTARGET_AND_CURRENT_PROFILE_INDEX 0xd0200014 594#define ixTARGET_AND_CURRENT_PROFILE_INDEX_1 0xd02000f0 595#define ixTARGET_AND_CURRENT_PROFILE_INDEX_2 0xd02000f4 596#define ixCG_FREQ_TRAN_VOTING_0 0xd02001a8 597#define ixCG_FREQ_TRAN_VOTING_1 0xd02001ac 598#define ixCG_FREQ_TRAN_VOTING_2 0xd02001b0 599#define ixCG_FREQ_TRAN_VOTING_3 0xd02001b4 600#define ixCG_FREQ_TRAN_VOTING_4 0xd02001b8 601#define ixCG_FREQ_TRAN_VOTING_5 0xd02001bc 602#define ixCG_FREQ_TRAN_VOTING_6 0xd02001c0 603#define ixCG_FREQ_TRAN_VOTING_7 0xd02001c4 604#define ixCG_STATIC_SCREEN_PARAMETER 0xd0200044 605#define ixCG_ACPI_CNTL 0xd0200064 606#define ixSCLK_DEEP_SLEEP_CNTL 0xd0200080 607#define ixSCLK_DEEP_SLEEP_CNTL2 0xd0200084 608#define ixSCLK_DEEP_SLEEP_CNTL3 0xd020009c 609#define ixSCLK_DEEP_SLEEP_MISC_CNTL 0xd0200088 610#define ixLCLK_DEEP_SLEEP_CNTL 0xd020008c 611#define ixLCLK_DEEP_SLEEP_CNTL2 0xd0200310 612#define ixSMU_VOLTAGE_STATUS 0xd0200094 613#define ixCG_ULV_PARAMETER 0xd020015c 614#define ixPWR_DC_RESP 0xd0200300 615#define ixPWR_VCE_RESP 0xd0200304 616#define ixPWR_UVD_RESP 0xd0200308 617#define ixPWR_ACP_RESP 0xd020030c 618#define ixPWR_DC_REQ 0xd020031c 619#define ixSCLK_MIN_DIV 0xd02003ac 620#define ixPCIE_PGFSM_CONFIG 0xd02002d0 621#define ixPCIE_PGFSM_WRITE 0xd02002d4 622#define ixSERDES_BUSY 0xd02002d8 623#define ixPCIE_PGFSM2_CONFIG 0xd02002dc 624#define ixPCIE_PGFSM2_WRITE 0xd02002e0 625#define ixSERDES2_BUSY 0xd02002e4 626#define ixPCIE_PGFSM_0_READ 0xd02002e8 627#define ixPCIE_PGFSM_1_READ 0xd02002ec 628#define ixPWR_ACPI_INTERRUPT 0xd0200318 629#define ixVDDGFX_IDLE_PARAMETER 0xd020036c 630#define ixVDDGFX_IDLE_CONTROL 0xd0200370 631#define ixVDDGFX_IDLE_EXIT 0xd0200374 632#define ixREG_SCLK_DEEP_SLEEP_EXIT 0xd0200378 633#define ixCAC_WEIGHT_LKG_DC_3 0xd020803c 634#define ixLCAC_MC0_CNTL 0xd0208130 635#define ixLCAC_MC0_OVR_SEL 0xd0208134 636#define ixLCAC_MC0_OVR_VAL 0xd0208138 637#define ixLCAC_MC1_CNTL 0xd020813c 638#define ixLCAC_MC1_OVR_SEL 0xd0208140 639#define ixLCAC_MC1_OVR_VAL 0xd0208144 640#define ixLCAC_MC2_CNTL 0xd0208148 641#define ixLCAC_MC2_OVR_SEL 0xd020814c 642#define ixLCAC_MC2_OVR_VAL 0xd0208150 643#define ixLCAC_MC3_CNTL 0xd0208154 644#define ixLCAC_MC3_OVR_SEL 0xd0208158 645#define ixLCAC_MC3_OVR_VAL 0xd020815c 646#define ixLCAC_CPL_CNTL 0xd0208160 647#define ixLCAC_CPL_OVR_SEL 0xd0208164 648#define ixLCAC_CPL_OVR_VAL 0xd0208168 649#define ixMISC_UNB_PWRMGT_CFG0 0xd020c000 650#define ixMISC_UNB_PWRMGT_CFG1 0xd020c004 651#define ixMISC_UNB_PWRMGT_DATA 0xd020c00c 652#define ixGNBPM_SMU_PWRMGT_DATA 0xd020c010 653#define ixDMA_ACTIVE_SAMPLER_CFG 0xd020c014 654#define ixSOUTHBRIDGE_TYPE 0xd020c01c 655#define ixGNBPM_SMU_PWRMGT_STATUS 0xd020c020 656#define ixALLOW_SR_INTR_CTRL 0xd020c024 657#define mmGC_CAC_LKG_AGGR_LOWER 0x3294 658#define mmGC_CAC_LKG_AGGR_UPPER 0x3295 659#define ixGC_CAC_WEIGHT_CU_0 0x32 660#define ixGC_CAC_WEIGHT_CU_1 0x33 661#define ixGC_CAC_WEIGHT_CU_2 0x34 662#define ixGC_CAC_WEIGHT_CU_3 0x35 663#define ixGC_CAC_ACC_CU0 0xba 664#define ixGC_CAC_ACC_CU1 0xbb 665#define ixGC_CAC_ACC_CU2 0xbc 666#define ixGC_CAC_ACC_CU3 0xbd 667#define ixGC_CAC_ACC_CU4 0xbe 668#define ixGC_CAC_ACC_CU5 0xbf 669#define ixGC_CAC_ACC_CU6 0xc0 670#define ixGC_CAC_ACC_CU7 0xc1 671#define ixGC_CAC_OVRD_CU 0xe7 672 673#endif /* SMU_8_0_D_H */ 674