Searched refs:ixLCAC_MC1_OVR_SEL (Results 1 - 9 of 9) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/smu/
H A Dsmu_6_0_d.h32 #define ixLCAC_MC1_OVR_SEL 0x0120 macro
H A Dsmu_8_0_d.h638 #define ixLCAC_MC1_OVR_SEL 0xd0208140 macro
H A Dsmu_7_0_0_d.h731 #define ixLCAC_MC1_OVR_SEL 0xc0400d40 macro
H A Dsmu_7_1_3_d.h1114 #define ixLCAC_MC1_OVR_SEL 0xc0400140 macro
H A Dsmu_7_1_2_d.h1182 #define ixLCAC_MC1_OVR_SEL 0xc0400140 macro
H A Dsmu_7_1_0_d.h1250 #define ixLCAC_MC1_OVR_SEL 0xc0400d40 macro
H A Dsmu_7_0_1_d.h1221 #define ixLCAC_MC1_OVR_SEL 0xc0400d40 macro
H A Dsmu_7_1_1_d.h1031 #define ixLCAC_MC1_OVR_SEL 0xc0400140 macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_kv_dpm.c547 WREG32_SMC(ixLCAC_MC1_OVR_SEL, 0);

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