Searched refs:ixLCAC_MC1_CNTL (Results 1 - 9 of 9) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/smu/
H A Dsmu_6_0_d.h31 #define ixLCAC_MC1_CNTL 0x011F macro
H A Dsmu_8_0_d.h637 #define ixLCAC_MC1_CNTL 0xd020813c macro
H A Dsmu_7_0_0_d.h730 #define ixLCAC_MC1_CNTL 0xc0400d3c macro
H A Dsmu_7_1_3_d.h1113 #define ixLCAC_MC1_CNTL 0xc040013c macro
H A Dsmu_7_1_2_d.h1181 #define ixLCAC_MC1_CNTL 0xc040013c macro
H A Dsmu_7_1_0_d.h1249 #define ixLCAC_MC1_CNTL 0xc0400d3c macro
H A Dsmu_7_0_1_d.h1220 #define ixLCAC_MC1_CNTL 0xc0400d3c macro
H A Dsmu_7_1_1_d.h1030 #define ixLCAC_MC1_CNTL 0xc040013c macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
H A Damdgpu_smu7_hwmgr.c1130 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5);
1135 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400009);
1138 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005);

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