Searched refs:ixLCAC_MC0_OVR_SEL (Results 1 - 9 of 9) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/smu/
H A Dsmu_6_0_d.h29 #define ixLCAC_MC0_OVR_SEL 0x011D macro
H A Dsmu_8_0_d.h635 #define ixLCAC_MC0_OVR_SEL 0xd0208134 macro
H A Dsmu_7_0_0_d.h728 #define ixLCAC_MC0_OVR_SEL 0xc0400d34 macro
H A Dsmu_7_1_3_d.h1111 #define ixLCAC_MC0_OVR_SEL 0xc0400134 macro
H A Dsmu_7_1_2_d.h1179 #define ixLCAC_MC0_OVR_SEL 0xc0400134 macro
H A Dsmu_7_1_0_d.h1247 #define ixLCAC_MC0_OVR_SEL 0xc0400d34 macro
H A Dsmu_7_0_1_d.h1218 #define ixLCAC_MC0_OVR_SEL 0xc0400d34 macro
H A Dsmu_7_1_1_d.h1028 #define ixLCAC_MC0_OVR_SEL 0xc0400134 macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_kv_dpm.c543 WREG32_SMC(ixLCAC_MC0_OVR_SEL, 0);

Completed in 306 milliseconds