/netbsd-current/sys/external/bsd/drm2/dist/drm/radeon/ |
H A D | radeon_uvd_v4_2.c | 52 addr = (rdev->uvd.gpu_addr + 0x200) >> 3; 54 addr = rdev->uvd.gpu_addr >> 3; 72 addr = (rdev->uvd.gpu_addr >> 28) & 0xF; 76 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF;
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H A D | radeon_uvd_v3_1.c | 49 uint64_t addr = semaphore->gpu_addr;
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H A D | radeon_semaphore.c | 56 (*semaphore)->gpu_addr = radeon_sa_bo_gpu_addr((*semaphore)->sa_bo); 74 ring->last_semaphore_signal_addr = semaphore->gpu_addr; 91 ring->last_semaphore_wait_addr = semaphore->gpu_addr;
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H A D | radeon_r600_dma.c | 149 upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF); 151 ((rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFFFFFFFC)); 156 WREG32(DMA_RB_BASE, ring->gpu_addr >> 8); 241 u64 gpu_addr; local 248 gpu_addr = rdev->wb.gpu_addr + index; 259 radeon_ring_write(ring, lower_32_bits(gpu_addr)); 260 radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xff); 295 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; 322 u64 addr = semaphore->gpu_addr; 348 u64 gpu_addr; local [all...] |
H A D | radeon_uvd_v2_2.c | 48 uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr; 82 uint64_t addr = semaphore->gpu_addr; 118 addr = rdev->uvd.gpu_addr >> 3; 135 addr = (rdev->uvd.gpu_addr >> 28) & 0xF; 139 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF;
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H A D | radeon_uvd_v1_0.c | 90 uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr; 126 addr = (rdev->uvd.gpu_addr >> 3) + 16; 143 addr = (rdev->uvd.gpu_addr >> 28) & 0xF; 147 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; 369 WREG32(UVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) | 379 WREG32(UVD_RBC_RB_BASE, ring->gpu_addr); 492 radeon_ring_write(ring, ib->gpu_addr);
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H A D | radeon_evergreen_dma.c | 50 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; 94 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); 95 radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));
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H A D | radeon_object.h | 137 extern int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr); 139 u64 max_offset, u64 *gpu_addr); 168 return sa_bo->manager->gpu_addr + sa_bo->soffset;
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H A D | radeon_cik_sdma.c | 160 radeon_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */ 161 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr)); 209 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; 238 u64 addr = semaphore->gpu_addr; 406 upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 408 ((rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC)); 413 WREG32(SDMA0_GFX_RB_BASE + reg_offset, ring->gpu_addr >> 8); 414 WREG32(SDMA0_GFX_RB_BASE_HI + reg_offset, ring->gpu_addr >> 40); 657 u64 gpu_addr; local 664 gpu_addr 714 u64 gpu_addr; local [all...] |
H A D | radeon_trace.h | 179 __field(uint64_t, gpu_addr) 185 __entry->gpu_addr = sem->gpu_addr; 189 __entry->waiters, __entry->gpu_addr)
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H A D | radeon_vce_v1_0.c | 223 uint64_t addr = rdev->vce.gpu_addr; 305 WREG32(VCE_RB_BASE_LO, ring->gpu_addr); 306 WREG32(VCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 312 WREG32(VCE_RB_BASE_LO2, ring->gpu_addr); 313 WREG32(VCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
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H A D | radeon_ni_dma.c | 150 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); 151 radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); 228 upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFF); 230 ((rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC)); 235 WREG32(DMA_RB_BASE + reg_offset, ring->gpu_addr >> 8);
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/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdkfd/ |
H A D | kfd_mqd_manager.c | 62 mqd_mem_obj->gpu_addr = dev->dqm->hiq_sdma_mqd.gpu_addr; 87 mqd_mem_obj->gpu_addr = dev->dqm->hiq_sdma_mqd.gpu_addr + offset;
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H A D | kfd_kernel_queue.c | 96 kq->pq_gpu_addr = kq->pq->gpu_addr; 104 kq->eop_gpu_addr = kq->eop_mem->gpu_addr; 117 kq->rptr_gpu_addr = kq->rptr_mem->gpu_addr; 126 kq->wptr_gpu_addr = kq->wptr_mem->gpu_addr; 177 kq->fence_gpu_addr = kq->fence_mem_obj->gpu_addr;
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/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
H A D | amdgpu_ih.c | 108 ih->gpu_addr = dma_addr; 128 &ih->ring_obj, &ih->gpu_addr, 136 ih->wptr_addr = adev->wb.gpu_addr + wptr_offs * 4; 138 ih->rptr_addr = adev->wb.gpu_addr + rptr_offs * 4; 171 (void *)ih->ring, ih->gpu_addr); 175 amdgpu_bo_free_kernel(&ih->ring_obj, &ih->gpu_addr, 177 amdgpu_device_wb_free(adev, (ih->wptr_addr - ih->gpu_addr) / 4); 178 amdgpu_device_wb_free(adev, (ih->rptr_addr - ih->gpu_addr) / 4);
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H A D | amdgpu_virt.c | 186 if (!amdgpu_sriov_vf(adev) || adev->virt.mm_table.gpu_addr) 192 &adev->virt.mm_table.gpu_addr, 201 adev->virt.mm_table.gpu_addr, 213 if (!amdgpu_sriov_vf(adev) || !adev->virt.mm_table.gpu_addr) 217 &adev->virt.mm_table.gpu_addr, 219 adev->virt.mm_table.gpu_addr = 0;
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H A D | amdgpu_vce_v4_0.c | 163 uint64_t addr = table->gpu_addr; 241 lower_32_bits(ring->gpu_addr)); 243 upper_32_bits(ring->gpu_addr)); 269 adev->vce.gpu_addr >> 8); 272 (adev->vce.gpu_addr >> 40) & 0xff); 279 adev->vce.gpu_addr >> 8); 282 (adev->vce.gpu_addr >> 40) & 0xff); 285 adev->vce.gpu_addr >> 8); 288 (adev->vce.gpu_addr >> 40) & 0xff); 351 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_LO), ring->gpu_addr); [all...] |
H A D | amdgpu_vcn_v2_5.c | 409 lower_32_bits(adev->vcn.inst[i].gpu_addr)); 411 upper_32_bits(adev->vcn.inst[i].gpu_addr)); 420 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset)); 422 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset)); 428 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 430 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 464 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 467 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); 485 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); 488 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr [all...] |
H A D | amdgpu_vcn_v1_0.c | 312 lower_32_bits(adev->vcn.inst->gpu_addr)); 314 upper_32_bits(adev->vcn.inst->gpu_addr)); 324 lower_32_bits(adev->vcn.inst->gpu_addr + offset)); 326 upper_32_bits(adev->vcn.inst->gpu_addr + offset)); 332 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 334 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 382 lower_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0); 384 upper_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0); 394 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0); 396 upper_32_bits(adev->vcn.inst->gpu_addr [all...] |
H A D | amdgpu_sdma_v2_4.c | 269 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); 270 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 462 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 464 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); 468 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); 469 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); 560 u64 gpu_addr; local 566 gpu_addr = adev->wb.gpu_addr + (index * 4); 576 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 612 u64 gpu_addr; local [all...] |
H A D | amdgpu_vcn_v2_0.c | 324 lower_32_bits(adev->vcn.inst->gpu_addr)); 326 upper_32_bits(adev->vcn.inst->gpu_addr)); 336 lower_32_bits(adev->vcn.inst->gpu_addr + offset)); 338 upper_32_bits(adev->vcn.inst->gpu_addr + offset)); 344 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 346 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 381 lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect); 384 upper_32_bits(adev->vcn.inst->gpu_addr), 0, indirect); 402 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect); 405 upper_32_bits(adev->vcn.inst->gpu_addr [all...] |
H A D | amdgpu_vce.h | 39 uint64_t gpu_addr; member in struct:amdgpu_vce
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H A D | amdgpu_object.h | 243 u64 *gpu_addr, void **cpu_addr); 247 u64 *gpu_addr, void **cpu_addr); 251 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr, 298 return sa_bo->manager->gpu_addr + sa_bo->soffset;
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H A D | amdgpu_ih.h | 51 uint64_t gpu_addr; member in struct:amdgpu_ih_ring
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H A D | amdgpu_uvd.h | 45 uint64_t gpu_addr; member in struct:amdgpu_uvd_inst
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