Searched refs:cfgPCIE_LANE_10_EQUALIZATION_CNTL (Results 1 - 2 of 2) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/nbif/
H A Dnbif_6_1_offset.h169 #define cfgPCIE_LANE_10_EQUALIZATION_CNTL 0x0290 // duplicate macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_0_offset.h537 #define cfgPCIE_LANE_10_EQUALIZATION_CNTL 0x0290 macro

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