Searched refs:cfgBIFPLR3_0_PCIE_PORT_VC_CAP_REG1 (Results 1 - 1 of 1) sorted by relevance
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/nbio/ | ||
H A D | nbio_7_0_offset.h | 2920 #define cfgBIFPLR3_0_PCIE_PORT_VC_CAP_REG1 0x0114 macro |
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