Searched refs:cfgBIFPLR2_0_PCIE_L1_PM_SUB_CNTL (Results 1 - 1 of 1) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_0_offset.h2815 #define cfgBIFPLR2_0_PCIE_L1_PM_SUB_CNTL 0x0378 macro

Completed in 226 milliseconds