| /netbsd-current/crypto/external/bsd/openssl.old/dist/crypto/md4/ |
| H A D | md4_dgst.c | 43 unsigned MD32_REG_T XX0, XX1, XX2, XX3, XX4, XX5, XX6, XX7, local
|
| /netbsd-current/crypto/external/bsd/openssl/dist/crypto/md4/ |
| H A D | md4_dgst.c | 49 unsigned MD32_REG_T XX0, XX1, XX2, XX3, XX4, XX5, XX6, XX7, local
|
| /netbsd-current/crypto/external/bsd/openssl.old/dist/crypto/md5/ |
| H A D | md5_dgst.c | 43 unsigned MD32_REG_T XX0, XX1, XX2, XX3, XX4, XX5, XX6, XX7, local
|
| /netbsd-current/crypto/external/bsd/openssl/dist/crypto/md5/ |
| H A D | md5_dgst.c | 49 unsigned MD32_REG_T XX0, XX1, XX2, XX3, XX4, XX5, XX6, XX7, local
|
| /netbsd-current/crypto/external/bsd/openssl.old/dist/crypto/sha/ |
| H A D | sha_local.h | 141 unsigned MD32_REG_T XX0, XX1, XX2, XX3, XX4, XX5, XX6, XX7, local
|
| /netbsd-current/crypto/external/bsd/openssl.old/dist/crypto/ripemd/ |
| H A D | rmd_dgst.c | 43 unsigned MD32_REG_T XX0, XX1, XX2, XX3, XX4, XX5, XX6, XX7, local
|
| /netbsd-current/crypto/external/bsd/openssl/dist/crypto/sha/ |
| H A D | sha_local.h | 142 unsigned MD32_REG_T XX0, XX1, XX2, XX3, XX4, XX5, XX6, XX7, local
|
| /netbsd-current/crypto/external/bsd/openssl/dist/crypto/ripemd/ |
| H A D | rmd_dgst.c | 49 unsigned MD32_REG_T XX0, XX1, XX2, XX3, XX4, XX5, XX6, XX7, local
|
| /netbsd-current/external/apache2/mDNSResponder/dist/mDNSCore/ |
| H A D | DNSDigest.c | 1030 unsigned MD32_REG_T XX0, XX1, XX2, XX3, XX4, XX5, XX6, XX7, local
|
| /netbsd-current/external/gpl3/gdb.old/dist/opcodes/ |
| H A D | ppc-opc.c | 1804 /* The XC field in an XX4 form instruction. This is split. */
3176 /* The XC field in an XX4 form instruction. This is split. */
3728 /* An XX4 form instruction. */
3729 #define XX4(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x3) << 4))
3800 /* The mask for an XX4 form instruction. */
3801 #define XX4_MASK XX4 (0x3f, 0x3)
8286 {"xxsel", XX4(60,3), XX4_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, XC6}},
8832 {"xxblendvb", P8RR|XX4(33,0), P_XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6}},
8833 {"xxblendvh", P8RR|XX4(33,1), P_XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6}},
8834 {"xxblendvw", P8RR|XX4(3
3727 #define XX4 macro
[all...] |
| /netbsd-current/external/gpl3/gdb/dist/opcodes/ |
| H A D | ppc-opc.c | 2316 /* The XC field in an XX4 form instruction. This is split. */
3878 /* The XC field in an XX4 form instruction. This is split. */
4481 /* An XX4 form instruction. */
4482 #define XX4(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x3) << 4))
4570 /* The mask for an XX4 form instruction. */
4571 #define XX4_MASK XX4 (0x3f, 0x3)
9235 {"xxsel", XX4(60,3), XX4_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, XC6}},
9786 {"xxblendvb", P8RR|XX4(33,0), P_XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6}},
9787 {"xxblendvh", P8RR|XX4(33,1), P_XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6}},
9788 {"xxblendvw", P8RR|XX4(3
4480 #define XX4 macro
[all...] |
| /netbsd-current/external/gpl3/binutils.old/dist/opcodes/ |
| H A D | ppc-opc.c | 2250 /* The XC field in an XX4 form instruction. This is split. */
3778 /* The XC field in an XX4 form instruction. This is split. */
4339 /* An XX4 form instruction. */
4340 #define XX4(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x3) << 4))
4420 /* The mask for an XX4 form instruction. */
4421 #define XX4_MASK XX4 (0x3f, 0x3)
8974 {"xxsel", XX4(60,3), XX4_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, XC6}},
9522 {"xxblendvb", P8RR|XX4(33,0), P_XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6}},
9523 {"xxblendvh", P8RR|XX4(33,1), P_XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6}},
9524 {"xxblendvw", P8RR|XX4(3
4338 #define XX4 macro
[all...] |
| /netbsd-current/external/gpl3/binutils/dist/opcodes/ |
| H A D | ppc-opc.c | 2316 /* The XC field in an XX4 form instruction. This is split. */
3878 /* The XC field in an XX4 form instruction. This is split. */
4481 /* An XX4 form instruction. */
4482 #define XX4(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x3) << 4))
4570 /* The mask for an XX4 form instruction. */
4571 #define XX4_MASK XX4 (0x3f, 0x3)
9235 {"xxsel", XX4(60,3), XX4_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, XC6}},
9786 {"xxblendvb", P8RR|XX4(33,0), P_XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6}},
9787 {"xxblendvh", P8RR|XX4(33,1), P_XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6}},
9788 {"xxblendvw", P8RR|XX4(3
4480 #define XX4 macro
[all...] |