Searched refs:X16 (Results 1 - 25 of 26) sorted by relevance

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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64SLSHardening.cpp165 // X16 and X17 are deliberately missing, as the mitigation requires those
180 // X30 is deliberately missing, for similar reasons as X16 and X17 are
230 // MOV X16, ThunkReg == ORR X16, XZR, ThunkReg, LSL #0
231 BuildMI(Entry, DebugLoc(), TII->get(AArch64::ORRXrs), AArch64::X16)
235 BuildMI(Entry, DebugLoc(), TII->get(AArch64::BR)).addReg(AArch64::X16);
276 // Since linkers are allowed to clobber X16 and X17 on function calls, the
278 // BLR X16 nor BLR X17. Code generation before must make sure that no BLR
279 // X16|X17 was produced if the mitigation is enabled.
291 assert(Reg != AArch64::X16
[all...]
H A DAArch64AsmPrinter.cpp292 // LDR X16,#12 ; X16 := addr of __xray_FunctionEntry or __xray_FunctionExit
293 // BLR X16 ; call the tracing trampoline
388 .addReg(AArch64::X16)
397 .addReg(AArch64::X16)
404 .addReg(AArch64::X16)
423 .addReg(AArch64::X16)
430 .addReg(AArch64::X16)
482 .addReg(AArch64::X16)
488 .addReg(AArch64::X16)
[all...]
H A DAArch64LowerHomogeneousPrologEpilog.cpp325 // Stash LR to X16
327 .addDef(AArch64::X16)
340 .addReg(Type == FrameHelperType::Epilog ? AArch64::X16 : AArch64::LR);
378 // Bail-out if X16 is live across the epilog helper because it is used in
386 if (SuccMBB->isLiveIn(AArch64::W16) || SuccMBB->isLiveIn(AArch64::X16))
H A DAArch64ExpandPseudoInsts.cpp727 BuildMI(MBB, MBBI, DL, TII->get(Opc), AArch64::X16)
732 BuildMI(MBB, MBBI, DL, TII->get(AArch64::MOVKXi), AArch64::X16)
733 .addUse(AArch64::X16)
746 .addUse(AArch64::X16)
H A DAArch64SpeculationHardening.cpp31 // relative abundance of registers, one register is reserved (X16) to be
32 // the taint register. X16 is expected to not clash with other register
34 // . The AArch64 ABI doesn't guarantee X16 to be retained across any call.
35 // . The only way to request X16 to be used as a programmer is through
37 // use X16/W16, this pass falls back to hardening against speculation
63 // the taint register X16 to be encoded in the SP register as value 0.
88 // function for some niche reason makes use of X16/W16.
656 MisspeculatingTaintReg = AArch64::X16;
H A DAArch64FrameLowering.cpp1341 .addReg(AArch64::X16, RegState::Implicit | RegState::Define | RegState::Dead)
1353 .addReg(AArch64::X16, RegState::Define)
1364 .addReg(AArch64::X16, RegState::Kill)
1366 .addReg(AArch64::X16, RegState::Implicit | RegState::Define | RegState::Dead)
H A DAArch64InstrInfo.cpp6353 Reg != AArch64::X16 && // X16 is not guaranteed to be preserved.
6914 Reg != AArch64::X16 && Reg != AArch64::X17 && LRU.available(Reg)) {
/netbsd-current/external/gpl3/gdb.old/dist/sim/testsuite/sim/bfin/
H A Dlmu_excpt_default.S243 X16: A0 = 0 || NOP || R1 = [ I1 ]; // Exception should occur here label
250 CHECKREG_SYM(r7, X16, r0); // RETX X16: (HARDCODED ADDR!!)
H A Dlmu_excpt_align.S278 X16: A0 = 0 || NOP || R1 = [ I1 ]; // Exception should occur here label
282 CHECKREG_SYM(r7, X16, r0); // RETX should be value of X16 (HARDCODED ADDR!!)
/netbsd-current/external/gpl3/gcc.old/dist/libstdc++-v3/include/ext/
H A Dtypelist.h375 #define _GLIBCXX_TYPELIST_CHAIN17(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16) __gnu_cxx::typelist::chain<X0, _GLIBCXX_TYPELIST_CHAIN16(X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16) >
376 #define _GLIBCXX_TYPELIST_CHAIN18(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17) __gnu_cxx::typelist::chain<X0, _GLIBCXX_TYPELIST_CHAIN17(X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17) >
377 #define _GLIBCXX_TYPELIST_CHAIN19(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18) __gnu_cxx::typelist::chain<X0, _GLIBCXX_TYPELIST_CHAIN18(X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18) >
378 #define _GLIBCXX_TYPELIST_CHAIN20(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19) __gnu_cxx::typelist::chain<X0, _GLIBCXX_TYPELIST_CHAIN19(X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19) >
/netbsd-current/external/gpl3/gcc/dist/libstdc++-v3/include/ext/
H A Dtypelist.h375 #define _GLIBCXX_TYPELIST_CHAIN17(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16) __gnu_cxx::typelist::chain<X0, _GLIBCXX_TYPELIST_CHAIN16(X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16) >
376 #define _GLIBCXX_TYPELIST_CHAIN18(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17) __gnu_cxx::typelist::chain<X0, _GLIBCXX_TYPELIST_CHAIN17(X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17) >
377 #define _GLIBCXX_TYPELIST_CHAIN19(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18) __gnu_cxx::typelist::chain<X0, _GLIBCXX_TYPELIST_CHAIN18(X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18) >
378 #define _GLIBCXX_TYPELIST_CHAIN20(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19) __gnu_cxx::typelist::chain<X0, _GLIBCXX_TYPELIST_CHAIN19(X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19) >
/netbsd-current/external/gpl3/gdb/dist/sim/testsuite/bfin/
H A Dlmu_excpt_default.S243 X16: A0 = 0 || NOP || R1 = [ I1 ]; // Exception should occur here label
250 CHECKREG_SYM(r7, X16, r0); // RETX X16: (HARDCODED ADDR!!)
H A Dlmu_excpt_align.S278 X16: A0 = 0 || NOP || R1 = [ I1 ]; // Exception should occur here label
282 CHECKREG_SYM(r7, X16, r0); // RETX should be value of X16 (HARDCODED ADDR!!)
/netbsd-current/sys/arch/sparc/fpu/
H A Dfpu.c96 #define X16(x) X8(x),X8(x) macro
103 X16(FSR_NV)
110 X16(FPE_FLTINV)
117 X16(FPE_FLTOPERR_TRAP)
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/Utils/
H A DAArch64BaseInfo.h47 case AArch64::X16: return AArch64::W16;
87 case AArch64::W16: return AArch64::X16;
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCTargetDesc.cpp117 {codeview::RegisterId::ARM64_X16, AArch64::X16},
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVFrameLowering.cpp794 RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17,
H A DRISCVISelLowering.cpp6607 RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17
7103 RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X7, RISCV::X28,
8088 .Case("{a6}", RISCV::X16)
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp436 AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19,
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp1195 if (IsRV32E && RegNo >= RISCV::X16 && RegNo <= RISCV::X31)
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCFrameLowering.cpp155 {PPC::X16, -128}, \
/netbsd-current/external/gpl3/binutils/dist/opcodes/
H A Dnds32-asm.c1455 {"l1i_ix_wtag", 0X15, 0}, {"l1i_ix_wwd", 0X16, 0},
/netbsd-current/external/gpl3/binutils.old/dist/opcodes/
H A Dnds32-asm.c1455 {"l1i_ix_wtag", 0X15, 0}, {"l1i_ix_wwd", 0X16, 0},
/netbsd-current/external/gpl3/gdb.old/dist/opcodes/
H A Dnds32-asm.c1455 {"l1i_ix_wtag", 0X15, 0}, {"l1i_ix_wwd", 0X16, 0},
/netbsd-current/external/gpl3/gdb/dist/opcodes/
H A Dnds32-asm.c1455 {"l1i_ix_wtag", 0X15, 0}, {"l1i_ix_wwd", 0X16, 0},

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