1//Original:/proj/frio/dv/testcases/lmu/lmu_excpt_default/lmu_excpt_default.dsp 2// Description: Default protection checks (CPLB disabled) 3// - MMR access in User mode 4// - DAG1 Access MMRs (supv/user mode, read/write) 5// - DAG1 Access Scratch SRAM (user or supervisor mode, read/write) 6# mach: bfin 7# sim: --environment operating 8 9#include "test.h" 10.include "testutils.inc" 11start 12 13include(selfcheck.inc) 14include(std.inc) 15include(mmrs.inc) 16 17#define EXCPT_PROTVIOL 0x23 18#define OMODE_SUPV 0 // not used in the hardware 19 20 21 22 CHECK_INIT(p5, 0xE0000000); 23 24 // setup interrupt controller with exception handler address 25 WR_MMR_LABEL(EVT3, handler, p0, r1); 26 WR_MMR_LABEL(EVT15, Supv, p0, r1); 27 WR_MMR(EVT_IMASK, 0xFFFFFFFF, p0, r0); 28 WR_MMR(EVT_OVERRIDE, 0x00000000, p0, r0); 29 CSYNC; 30 31 A0 = 0; 32 33 // go to user mode. and enable exceptions 34 LD32_LABEL(r0, User); 35 RETI = R0; 36 37 // But first raise interrupt 15 so we can run in supervisor mode. 38 RAISE 15; 39 40 RTI; 41 42Supv: 43 44 //------------------------------------------------------- 45 // DAG1 MMR Write access 46 47 48 49 LD32(i1, (DCPLB_ADDR0)); 50 LD32_LABEL(p2, Y01); // Exception handler will return to this address 51 LD32(r0, 0xdeadbeef); 52 53 54 R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first 55X01: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 56Y01: 57 58 // Now check that handler read correct values 59 CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT 60 CHECKREG(r5, DCPLB_ADDR0); // FAULT ADDRESS 61 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV)); // DCPLB_STATUS 62 CHECKREG_SYM(r7, X01, r0); // RETX X01: (HARDCODED ADDR!!) 63 64 //------------------------------------------------------- 65 // DAG1 MMR Read access 66 67 68 69 LD32(i1, (DCPLB_ADDR1)); 70 LD32_LABEL(p2, Y02); // Exception handler will return to this address 71 72 73 R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first 74X02: A0 = 0 || NOP || R1 = [ I1 ]; // Exception should occur here 75Y02: 76 77 // Now check that handler read correct values 78 CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT 79 CHECKREG(r5, DCPLB_ADDR1); // FAULT ADDRESS 80 CHECKREG(r6, (FAULT_READ|FAULT_DAG1|FAULT_SUPV)); // DCPLB_STATUS 81 CHECKREG_SYM(r7, X02, r0); // RETX X02: (HARDCODED ADDR!!) 82 83#if 0 84 //------------------------------------------------------- 85 // DAG1 Scratch SRAM Write access 86 87 88 89 LD32(i1, (( 0xFF800000 + 0x300000))); 90 LD32_LABEL(p2, Y03); // Exception handler will return to this address 91 LD32(r1, 0xdeadbeef); 92 93 94 R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first 95X03: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 96Y03: 97 98 // Now check that handler read correct values 99 CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT 100 CHECKREG(r5, ( 0xFF800000 + 0x300000)); // FAULT ADDRESS 101 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_SUPV)); // DCPLB_STATUS 102 CHECKREG_SYM(r7, X03, r0); // RETX X03: (HARDCODED ADDR!!) 103 104 //------------------------------------------------------- 105 // DAG1 Scratch SRAM Read access 106 107 108 109 LD32(i1, ((( 0xFF800000 + 0x300000) + 4))); 110 LD32_LABEL(p2, Y04); // Exception handler will return to this address 111 112 113 R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first 114X04: A0 = 0 || NOP || R1 = [ I1 ]; // Exception should occur here 115Y04: 116 117 // Now check that handler read correct values 118 CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT 119 CHECKREG(r5, (( 0xFF800000 + 0x300000) + 4)); // FAULT ADDRESS 120 CHECKREG(r6, (FAULT_READ|FAULT_DAG1|FAULT_SUPV)); // DCPLB_STATUS 121 CHECKREG_SYM(r7, X04, r0); // RETX X04: (HARDCODED ADDR!!) 122#endif 123 124 //------------------------------------------------------- 125 126 // Now, go to User mode 127 LD32_LABEL(r0, User); 128 RETI = R0; 129 RTI; 130 131 132User: 133 134 //------------------------------------------------------- 135 // DAG0 MMR Write access (multi-issue) 136 137 138 139 LD32(i1, (DCPLB_ADDR0)); 140 LD32_LABEL(p2, Y11); // Exception handler will return to this address 141 LD32(r0, 0xdeadbeef); 142 143 144 R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first 145X11: A0 = 0 || [ I1 ] = R1 || NOP; // Exception should occur here 146Y11: 147 148 // Now check that handler read correct values 149 CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT 150 CHECKREG(r5, DCPLB_ADDR0); // FAULT ADDRESS 151 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_USER)); // DCPLB_STATUS 152 CHECKREG_SYM(r7, X11, r0); // RETX X11: (HARDCODED ADDR!!) 153 154 //------------------------------------------------------- 155 // DAG0 MMR Read access (multi-issue) 156 157 158 159 LD32(i1, (DCPLB_ADDR1)); 160 LD32_LABEL(p2, Y12); // Exception handler will return to this address 161 162 163 R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first 164X12: A0 = 0 || R1 = [ I1 ] || NOP; // Exception should occur here 165Y12: 166 167 // Now check that handler read correct values 168 CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT 169 CHECKREG(r5, DCPLB_ADDR1); // FAULT ADDRESS 170 CHECKREG(r6, (FAULT_READ|FAULT_DAG0|FAULT_USER)); // DCPLB_STATUS 171 CHECKREG_SYM(r7, X12, r0); // RETX X12: (HARDCODED ADDR!!) 172 173 //------------------------------------------------------- 174 // DAG1 MMR Write access 175 176 177 178 LD32(i1, (DCPLB_ADDR0)); 179 LD32_LABEL(p2, Y13); // Exception handler will return to this address 180 LD32(r0, 0xdeadbeef); 181 182 183 R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first 184X13: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 185Y13: 186 187 // Now check that handler read correct values 188 CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT 189 CHECKREG(r5, DCPLB_ADDR0); // FAULT ADDRESS 190 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_USER)); // DCPLB_STATUS 191 CHECKREG_SYM(r7, X13, r0); // RETX X13: (HARDCODED ADDR!!) 192 193 //------------------------------------------------------- 194 // DAG1 MMR Read access 195 196 197 198 LD32(i1, (DCPLB_ADDR1)); 199 LD32_LABEL(p2, Y14); // Exception handler will return to this address 200 201 202 R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first 203X14: A0 = 0 || NOP || R1 = [ I1 ]; // Exception should occur here 204Y14: 205 206 // Now check that handler read correct values 207 CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT 208 CHECKREG(r5, DCPLB_ADDR1); // FAULT ADDRESS 209 CHECKREG(r6, (FAULT_READ|FAULT_DAG1|FAULT_USER)); // DCPLB_STATUS 210 CHECKREG_SYM(r7, X14, r0); // RETX X14: (HARDCODED ADDR!!) 211 212#if 0 213 //------------------------------------------------------- 214 // DAG1 Scratch SRAM Write access 215 216 217 218 LD32(i1, (( 0xFF800000 + 0x300000))); 219 LD32_LABEL(p2, Y15); // Exception handler will return to this address 220 LD32(r1, 0xdeadbeef); 221 222 223 R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first 224X15: A0 = 0 || NOP || [ I1 ] = R1; // Exception should occur here 225Y15: 226 227 // Now check that handler read correct values 228 CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT 229 CHECKREG(r5, ( 0xFF800000 + 0x300000)); // FAULT ADDRESS 230 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG1|FAULT_USER)); // DCPLB_STATUS 231 CHECKREG_SYM(r7, X15, r0); // RETX X15: (HARDCODED ADDR!!) 232 233 //------------------------------------------------------- 234 // DAG1 Scratch SRAM Read access 235 236 237 238 LD32(i1, ((( 0xFF800000 + 0x300000) + 4))); 239 LD32_LABEL(p2, Y16); // Exception handler will return to this address 240 241 242 R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first 243X16: A0 = 0 || NOP || R1 = [ I1 ]; // Exception should occur here 244Y16: 245 246 // Now check that handler read correct values 247 CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT 248 CHECKREG(r5, (( 0xFF800000 + 0x300000) + 4)); // FAULT ADDRESS 249 CHECKREG(r6, (FAULT_READ|FAULT_DAG1|FAULT_USER)); // DCPLB_STATUS 250 CHECKREG_SYM(r7, X16, r0); // RETX X16: (HARDCODED ADDR!!) 251#endif 252 253 //------------------------------------------------------- 254 // DAG0 MMR Write access (single-issue) 255 256 257 258 LD32(i1, (DCPLB_ADDR0)); 259 LD32_LABEL(p2, Y17); // Exception handler will return to this address 260 LD32(r0, 0xdeadbeef); 261 262 263 R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first 264X17: [ I1 ] = R1; // Exception should occur here 265Y17: 266 267 // Now check that handler read correct values 268 CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT 269 CHECKREG(r5, DCPLB_ADDR0); // FAULT ADDRESS 270 CHECKREG(r6, (FAULT_WRITE|FAULT_DAG0|FAULT_USER)); // DCPLB_STATUS 271 CHECKREG_SYM(r7, X17, r0); // RETX X17: (HARDCODED ADDR!!) 272 273 //------------------------------------------------------- 274 // DAG0 MMR Read access (single-issue) 275 276 277 278 LD32(i1, (DCPLB_ADDR1)); 279 LD32_LABEL(p2, Y18); // Exception handler will return to this address 280 281 282 R4 = 0;R5 = 0;R6 = 0;R7 = 0; // Exception handler will set these, reset them first 283X18: R1 = [ I1 ]; // Exception should occur here 284Y18: 285 286 // Now check that handler read correct values 287 CHECKREG(r4, (OMODE_SUPV|EXCPT_PROTVIOL)); // SEQSTAT 288 CHECKREG(r5, DCPLB_ADDR1); // FAULT ADDRESS 289 CHECKREG(r6, (FAULT_READ|FAULT_DAG0|FAULT_USER)); // DCPLB_STATUS 290 CHECKREG_SYM(r7, X18, r0); // RETX X18: (HARDCODED ADDR!!) 291 292 //------------------------------------------------------- 293 dbg_pass; 294 295 296handler: 297 R4 = SEQSTAT; // Get exception cause 298 299 // read and check fail addr (addr_which_causes_exception) 300 // should not be set for alignment exception 301 RD_MMR(DCPLB_FAULT_ADDR, p0, r5); 302 RD_MMR(DCPLB_STATUS, p0, r6); 303 R7 = RETX; // get address of excepting instruction 304 305 RETX = P2; 306 307 RTX; 308