Searched refs:VFP_uword (Results 1 - 6 of 6) sorted by relevance
/netbsd-current/external/gpl3/gdb.old/dist/sim/arm/ |
H A D | armsupp.c | 551 ARMul_StoreWordN (state, address, VFP_uword (src)); 579 ARMul_StoreWordN (state, address, VFP_uword (dest)); 633 ARMul_StoreWordN (state, address, VFP_uword (sreg)); 676 ARMul_StoreWordN (state, address, VFP_uword (src)); 732 VFP_uword (dest) = ARMul_LoadWordN (state, address); 782 VFP_uword (sreg) = ARMul_LoadWordN (state, address); 830 VFP_uword (dest) = ARMul_LoadWordN (state, address); 858 VFP_uword (dest) = ARMul_LoadWordN (state, address); 1507 VFP_uword (dest) = VFP_dval (srcM); 1514 VFP_uword (des [all...] |
H A D | armdefs.h | 65 #define VFP_uword(N) (state->VFP_Reg[(N)>> 1].uword[(N) & 1]) macro
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H A D | armemu.c | 1073 state->Reg[BITS (12, 15)] = VFP_uword (sreg); 1074 state->Reg[BITS (16, 19)] = VFP_uword (sreg + 1); 1078 VFP_uword (sreg) = state->Reg[BITS (12, 15)]; 1079 VFP_uword (sreg + 1) = state->Reg[BITS (16, 19)]; 1129 state->Reg[DESTReg] = VFP_uword (sreg); 1131 VFP_uword (sreg) = state->Reg[DESTReg]; 4644 state->Reg[BITS (12, 15)] = VFP_uword (BITS (16, 19) << 1 | BIT (7)); 4646 VFP_uword (BITS (16, 19) << 1 | BIT (7)) = state->Reg[BITS (12, 15)];
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/netbsd-current/external/gpl3/gdb/dist/sim/arm/ |
H A D | armsupp.c | 554 ARMul_StoreWordN (state, address, VFP_uword (src)); 582 ARMul_StoreWordN (state, address, VFP_uword (dest)); 636 ARMul_StoreWordN (state, address, VFP_uword (sreg)); 679 ARMul_StoreWordN (state, address, VFP_uword (src)); 735 VFP_uword (dest) = ARMul_LoadWordN (state, address); 785 VFP_uword (sreg) = ARMul_LoadWordN (state, address); 833 VFP_uword (dest) = ARMul_LoadWordN (state, address); 861 VFP_uword (dest) = ARMul_LoadWordN (state, address); 1510 VFP_uword (dest) = VFP_dval (srcM); 1517 VFP_uword (des [all...] |
H A D | armdefs.h | 65 #define VFP_uword(N) (state->VFP_Reg[(N)>> 1].uword[(N) & 1]) macro
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H A D | armemu.c | 1137 state->Reg[BITS (12, 15)] = VFP_uword (sreg); 1138 state->Reg[BITS (16, 19)] = VFP_uword (sreg + 1); 1142 VFP_uword (sreg) = state->Reg[BITS (12, 15)]; 1143 VFP_uword (sreg + 1) = state->Reg[BITS (16, 19)]; 1193 state->Reg[DESTReg] = VFP_uword (sreg); 1195 VFP_uword (sreg) = state->Reg[DESTReg]; 4708 state->Reg[BITS (12, 15)] = VFP_uword (BITS (16, 19) << 1 | BIT (7)); 4710 VFP_uword (BITS (16, 19) << 1 | BIT (7)) = state->Reg[BITS (12, 15)];
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