Searched refs:UVD_VCPU_INT_EN__SW_RB5_INT_EN__SHIFT (Results 1 - 2 of 2) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_0_0_sh_mask.h2224 #define UVD_VCPU_INT_EN__SW_RB5_INT_EN__SHIFT 0xa macro
H A Dvcn_2_5_sh_mask.h2229 #define UVD_VCPU_INT_EN__SW_RB5_INT_EN__SHIFT 0xa macro

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