1/* $NetBSD: vcn_2_5_sh_mask.h,v 1.2 2021/12/18 23:45:24 riastradh Exp $ */ 2 3/* 4 * Copyright (C) 2019 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24#ifndef _vcn_2_5_SH_MASK_HEADER 25#define _vcn_2_5_SH_MASK_HEADER 26 27// addressBlock: uvd0_mmsch_dec 28//MMSCH_UCODE_ADDR 29#define MMSCH_UCODE_ADDR__UCODE_ADDR__SHIFT 0x2 30#define MMSCH_UCODE_ADDR__UCODE_LOCK__SHIFT 0x1f 31#define MMSCH_UCODE_ADDR__UCODE_ADDR_MASK 0x00003FFCL 32#define MMSCH_UCODE_ADDR__UCODE_LOCK_MASK 0x80000000L 33//MMSCH_UCODE_DATA 34#define MMSCH_UCODE_DATA__UCODE_DATA__SHIFT 0x0 35#define MMSCH_UCODE_DATA__UCODE_DATA_MASK 0xFFFFFFFFL 36//MMSCH_SRAM_ADDR 37#define MMSCH_SRAM_ADDR__SRAM_ADDR__SHIFT 0x2 38#define MMSCH_SRAM_ADDR__SRAM_LOCK__SHIFT 0x1f 39#define MMSCH_SRAM_ADDR__SRAM_ADDR_MASK 0x00001FFCL 40#define MMSCH_SRAM_ADDR__SRAM_LOCK_MASK 0x80000000L 41//MMSCH_SRAM_DATA 42#define MMSCH_SRAM_DATA__SRAM_DATA__SHIFT 0x0 43#define MMSCH_SRAM_DATA__SRAM_DATA_MASK 0xFFFFFFFFL 44//MMSCH_VF_SRAM_OFFSET 45#define MMSCH_VF_SRAM_OFFSET__VF_SRAM_OFFSET__SHIFT 0x2 46#define MMSCH_VF_SRAM_OFFSET__VF_SRAM_NUM_DW_PER_VF__SHIFT 0x10 47#define MMSCH_VF_SRAM_OFFSET__VF_SRAM_OFFSET_MASK 0x00001FFCL 48#define MMSCH_VF_SRAM_OFFSET__VF_SRAM_NUM_DW_PER_VF_MASK 0x00FF0000L 49//MMSCH_DB_SRAM_OFFSET 50#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_OFFSET__SHIFT 0x2 51#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_ENG__SHIFT 0x10 52#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_RING_PER_ENG__SHIFT 0x18 53#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_OFFSET_MASK 0x00001FFCL 54#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_ENG_MASK 0x00FF0000L 55#define MMSCH_DB_SRAM_OFFSET__DB_SRAM_NUM_RING_PER_ENG_MASK 0xFF000000L 56//MMSCH_CTX_SRAM_OFFSET 57#define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_OFFSET__SHIFT 0x2 58#define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_SIZE__SHIFT 0x10 59#define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_OFFSET_MASK 0x00001FFCL 60#define MMSCH_CTX_SRAM_OFFSET__CTX_SRAM_SIZE_MASK 0xFFFF0000L 61//MMSCH_CTL 62#define MMSCH_CTL__P_RUNSTALL__SHIFT 0x0 63#define MMSCH_CTL__P_RESET__SHIFT 0x1 64#define MMSCH_CTL__VFID_FIFO_EN__SHIFT 0x4 65#define MMSCH_CTL__P_LOCK__SHIFT 0x1f 66#define MMSCH_CTL__P_RUNSTALL_MASK 0x00000001L 67#define MMSCH_CTL__P_RESET_MASK 0x00000002L 68#define MMSCH_CTL__VFID_FIFO_EN_MASK 0x00000010L 69#define MMSCH_CTL__P_LOCK_MASK 0x80000000L 70//MMSCH_INTR 71#define MMSCH_INTR__INTR__SHIFT 0x0 72#define MMSCH_INTR__INTR_MASK 0x00001FFFL 73//MMSCH_INTR_ACK 74#define MMSCH_INTR_ACK__INTR__SHIFT 0x0 75#define MMSCH_INTR_ACK__INTR_MASK 0x00001FFFL 76//MMSCH_INTR_STATUS 77#define MMSCH_INTR_STATUS__INTR__SHIFT 0x0 78#define MMSCH_INTR_STATUS__INTR_MASK 0x00001FFFL 79//MMSCH_VF_VMID 80#define MMSCH_VF_VMID__VF_CTX_VMID__SHIFT 0x0 81#define MMSCH_VF_VMID__VF_GPCOM_VMID__SHIFT 0x5 82#define MMSCH_VF_VMID__VF_CTX_VMID_MASK 0x0000001FL 83#define MMSCH_VF_VMID__VF_GPCOM_VMID_MASK 0x000003E0L 84//MMSCH_VF_CTX_ADDR_LO 85#define MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO__SHIFT 0x6 86#define MMSCH_VF_CTX_ADDR_LO__VF_CTX_ADDR_LO_MASK 0xFFFFFFC0L 87//MMSCH_VF_CTX_ADDR_HI 88#define MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI__SHIFT 0x0 89#define MMSCH_VF_CTX_ADDR_HI__VF_CTX_ADDR_HI_MASK 0xFFFFFFFFL 90//MMSCH_VF_CTX_SIZE 91#define MMSCH_VF_CTX_SIZE__VF_CTX_SIZE__SHIFT 0x0 92#define MMSCH_VF_CTX_SIZE__VF_CTX_SIZE_MASK 0xFFFFFFFFL 93//MMSCH_VF_GPCOM_ADDR_LO 94#define MMSCH_VF_GPCOM_ADDR_LO__VF_GPCOM_ADDR_LO__SHIFT 0x6 95#define MMSCH_VF_GPCOM_ADDR_LO__VF_GPCOM_ADDR_LO_MASK 0xFFFFFFC0L 96//MMSCH_VF_GPCOM_ADDR_HI 97#define MMSCH_VF_GPCOM_ADDR_HI__VF_GPCOM_ADDR_HI__SHIFT 0x0 98#define MMSCH_VF_GPCOM_ADDR_HI__VF_GPCOM_ADDR_HI_MASK 0xFFFFFFFFL 99//MMSCH_VF_GPCOM_SIZE 100#define MMSCH_VF_GPCOM_SIZE__VF_GPCOM_SIZE__SHIFT 0x0 101#define MMSCH_VF_GPCOM_SIZE__VF_GPCOM_SIZE_MASK 0xFFFFFFFFL 102//MMSCH_VF_MAILBOX_HOST 103#define MMSCH_VF_MAILBOX_HOST__DATA__SHIFT 0x0 104#define MMSCH_VF_MAILBOX_HOST__DATA_MASK 0xFFFFFFFFL 105//MMSCH_VF_MAILBOX_RESP 106#define MMSCH_VF_MAILBOX_RESP__RESP__SHIFT 0x0 107#define MMSCH_VF_MAILBOX_RESP__RESP_MASK 0xFFFFFFFFL 108//MMSCH_VF_MAILBOX_0 109#define MMSCH_VF_MAILBOX_0__DATA__SHIFT 0x0 110#define MMSCH_VF_MAILBOX_0__DATA_MASK 0xFFFFFFFFL 111//MMSCH_VF_MAILBOX_0_RESP 112#define MMSCH_VF_MAILBOX_0_RESP__RESP__SHIFT 0x0 113#define MMSCH_VF_MAILBOX_0_RESP__RESP_MASK 0xFFFFFFFFL 114//MMSCH_VF_MAILBOX_1 115#define MMSCH_VF_MAILBOX_1__DATA__SHIFT 0x0 116#define MMSCH_VF_MAILBOX_1__DATA_MASK 0xFFFFFFFFL 117//MMSCH_VF_MAILBOX_1_RESP 118#define MMSCH_VF_MAILBOX_1_RESP__RESP__SHIFT 0x0 119#define MMSCH_VF_MAILBOX_1_RESP__RESP_MASK 0xFFFFFFFFL 120//MMSCH_CNTL 121#define MMSCH_CNTL__CLK_EN__SHIFT 0x0 122#define MMSCH_CNTL__ED_ENABLE__SHIFT 0x1 123#define MMSCH_CNTL__MMSCH_IRQ_ERR__SHIFT 0x5 124#define MMSCH_CNTL__MMSCH_NACK_INTR_EN__SHIFT 0x9 125#define MMSCH_CNTL__MMSCH_DB_BUSY_INTR_EN__SHIFT 0xa 126#define MMSCH_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 127#define MMSCH_CNTL__TIMEOUT_DIS__SHIFT 0x1c 128#define MMSCH_CNTL__CLK_EN_MASK 0x00000001L 129#define MMSCH_CNTL__ED_ENABLE_MASK 0x00000002L 130#define MMSCH_CNTL__MMSCH_IRQ_ERR_MASK 0x000001E0L 131#define MMSCH_CNTL__MMSCH_NACK_INTR_EN_MASK 0x00000200L 132#define MMSCH_CNTL__MMSCH_DB_BUSY_INTR_EN_MASK 0x00000400L 133#define MMSCH_CNTL__PRB_TIMEOUT_VAL_MASK 0x0FF00000L 134#define MMSCH_CNTL__TIMEOUT_DIS_MASK 0x10000000L 135//MMSCH_NONCACHE_OFFSET0 136#define MMSCH_NONCACHE_OFFSET0__OFFSET__SHIFT 0x0 137#define MMSCH_NONCACHE_OFFSET0__OFFSET_MASK 0x0FFFFFFFL 138//MMSCH_NONCACHE_SIZE0 139#define MMSCH_NONCACHE_SIZE0__SIZE__SHIFT 0x0 140#define MMSCH_NONCACHE_SIZE0__SIZE_MASK 0x00FFFFFFL 141//MMSCH_NONCACHE_OFFSET1 142#define MMSCH_NONCACHE_OFFSET1__OFFSET__SHIFT 0x0 143#define MMSCH_NONCACHE_OFFSET1__OFFSET_MASK 0x0FFFFFFFL 144//MMSCH_NONCACHE_SIZE1 145#define MMSCH_NONCACHE_SIZE1__SIZE__SHIFT 0x0 146#define MMSCH_NONCACHE_SIZE1__SIZE_MASK 0x00FFFFFFL 147//MMSCH_PROC_STATE1 148#define MMSCH_PROC_STATE1__PC__SHIFT 0x0 149#define MMSCH_PROC_STATE1__PC_MASK 0xFFFFFFFFL 150//MMSCH_LAST_MC_ADDR 151#define MMSCH_LAST_MC_ADDR__MC_ADDR__SHIFT 0x0 152#define MMSCH_LAST_MC_ADDR__RW__SHIFT 0x1f 153#define MMSCH_LAST_MC_ADDR__MC_ADDR_MASK 0x0FFFFFFFL 154#define MMSCH_LAST_MC_ADDR__RW_MASK 0x80000000L 155//MMSCH_LAST_MEM_ACCESS_HI 156#define MMSCH_LAST_MEM_ACCESS_HI__PROC_CMD__SHIFT 0x0 157#define MMSCH_LAST_MEM_ACCESS_HI__FIFO_RPTR__SHIFT 0x8 158#define MMSCH_LAST_MEM_ACCESS_HI__FIFO_WPTR__SHIFT 0xc 159#define MMSCH_LAST_MEM_ACCESS_HI__PROC_CMD_MASK 0x00000007L 160#define MMSCH_LAST_MEM_ACCESS_HI__FIFO_RPTR_MASK 0x00000700L 161#define MMSCH_LAST_MEM_ACCESS_HI__FIFO_WPTR_MASK 0x00007000L 162//MMSCH_LAST_MEM_ACCESS_LO 163#define MMSCH_LAST_MEM_ACCESS_LO__PROC_ADDR__SHIFT 0x0 164#define MMSCH_LAST_MEM_ACCESS_LO__PROC_ADDR_MASK 0xFFFFFFFFL 165//MMSCH_IOV_ACTIVE_FCN_ID 166#define MMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_VF_ID__SHIFT 0x0 167#define MMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_PF_VF__SHIFT 0x1f 168#define MMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_VF_ID_MASK 0x0000001FL 169#define MMSCH_IOV_ACTIVE_FCN_ID__ACTIVE_PF_VF_MASK 0x80000000L 170//MMSCH_SCRATCH_0 171#define MMSCH_SCRATCH_0__SCRATCH_0__SHIFT 0x0 172#define MMSCH_SCRATCH_0__SCRATCH_0_MASK 0xFFFFFFFFL 173//MMSCH_SCRATCH_1 174#define MMSCH_SCRATCH_1__SCRATCH_1__SHIFT 0x0 175#define MMSCH_SCRATCH_1__SCRATCH_1_MASK 0xFFFFFFFFL 176//MMSCH_GPUIOV_SCH_BLOCK_0 177#define MMSCH_GPUIOV_SCH_BLOCK_0__ID__SHIFT 0x0 178#define MMSCH_GPUIOV_SCH_BLOCK_0__VERSION__SHIFT 0x4 179#define MMSCH_GPUIOV_SCH_BLOCK_0__SIZE__SHIFT 0x8 180#define MMSCH_GPUIOV_SCH_BLOCK_0__ID_MASK 0x0000000FL 181#define MMSCH_GPUIOV_SCH_BLOCK_0__VERSION_MASK 0x000000F0L 182#define MMSCH_GPUIOV_SCH_BLOCK_0__SIZE_MASK 0x0000FF00L 183//MMSCH_GPUIOV_CMD_CONTROL_0 184#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_TYPE__SHIFT 0x0 185#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE__SHIFT 0x4 186#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_INTR_EN__SHIFT 0x5 187#define MMSCH_GPUIOV_CMD_CONTROL_0__VM_BUSY_INTR_EN__SHIFT 0x6 188#define MMSCH_GPUIOV_CMD_CONTROL_0__FUNCTINO_ID__SHIFT 0x8 189#define MMSCH_GPUIOV_CMD_CONTROL_0__NEXT_FUNCTINO_ID__SHIFT 0x10 190#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_TYPE_MASK 0x0000000FL 191#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_MASK 0x00000010L 192#define MMSCH_GPUIOV_CMD_CONTROL_0__CMD_EXECUTE_INTR_EN_MASK 0x00000020L 193#define MMSCH_GPUIOV_CMD_CONTROL_0__VM_BUSY_INTR_EN_MASK 0x00000040L 194#define MMSCH_GPUIOV_CMD_CONTROL_0__FUNCTINO_ID_MASK 0x0000FF00L 195#define MMSCH_GPUIOV_CMD_CONTROL_0__NEXT_FUNCTINO_ID_MASK 0x00FF0000L 196//MMSCH_GPUIOV_CMD_STATUS_0 197#define MMSCH_GPUIOV_CMD_STATUS_0__CMD_STATUS__SHIFT 0x0 198#define MMSCH_GPUIOV_CMD_STATUS_0__CMD_STATUS_MASK 0x0000000FL 199//MMSCH_GPUIOV_VM_BUSY_STATUS_0 200#define MMSCH_GPUIOV_VM_BUSY_STATUS_0__BUSY__SHIFT 0x0 201#define MMSCH_GPUIOV_VM_BUSY_STATUS_0__BUSY_MASK 0xFFFFFFFFL 202//MMSCH_GPUIOV_ACTIVE_FCNS_0 203#define MMSCH_GPUIOV_ACTIVE_FCNS_0__ACTIVE_FCNS__SHIFT 0x0 204#define MMSCH_GPUIOV_ACTIVE_FCNS_0__ACTIVE_FCNS_MASK 0xFFFFFFFFL 205//MMSCH_GPUIOV_ACTIVE_FCN_ID_0 206#define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID__SHIFT 0x0 207#define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID_STATUS__SHIFT 0x8 208#define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID_MASK 0x000000FFL 209#define MMSCH_GPUIOV_ACTIVE_FCN_ID_0__ID_STATUS_MASK 0x00000F00L 210//MMSCH_GPUIOV_DW6_0 211#define MMSCH_GPUIOV_DW6_0__DATA__SHIFT 0x0 212#define MMSCH_GPUIOV_DW6_0__DATA_MASK 0xFFFFFFFFL 213//MMSCH_GPUIOV_DW7_0 214#define MMSCH_GPUIOV_DW7_0__DATA__SHIFT 0x0 215#define MMSCH_GPUIOV_DW7_0__DATA_MASK 0xFFFFFFFFL 216//MMSCH_GPUIOV_DW8_0 217#define MMSCH_GPUIOV_DW8_0__DATA__SHIFT 0x0 218#define MMSCH_GPUIOV_DW8_0__DATA_MASK 0xFFFFFFFFL 219//MMSCH_GPUIOV_SCH_BLOCK_1 220#define MMSCH_GPUIOV_SCH_BLOCK_1__ID__SHIFT 0x0 221#define MMSCH_GPUIOV_SCH_BLOCK_1__VERSION__SHIFT 0x4 222#define MMSCH_GPUIOV_SCH_BLOCK_1__SIZE__SHIFT 0x8 223#define MMSCH_GPUIOV_SCH_BLOCK_1__ID_MASK 0x0000000FL 224#define MMSCH_GPUIOV_SCH_BLOCK_1__VERSION_MASK 0x000000F0L 225#define MMSCH_GPUIOV_SCH_BLOCK_1__SIZE_MASK 0x0000FF00L 226//MMSCH_GPUIOV_CMD_CONTROL_1 227#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_TYPE__SHIFT 0x0 228#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE__SHIFT 0x4 229#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_INTR_EN__SHIFT 0x5 230#define MMSCH_GPUIOV_CMD_CONTROL_1__VM_BUSY_INTR_EN__SHIFT 0x6 231#define MMSCH_GPUIOV_CMD_CONTROL_1__FUNCTINO_ID__SHIFT 0x8 232#define MMSCH_GPUIOV_CMD_CONTROL_1__NEXT_FUNCTINO_ID__SHIFT 0x10 233#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_TYPE_MASK 0x0000000FL 234#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_MASK 0x00000010L 235#define MMSCH_GPUIOV_CMD_CONTROL_1__CMD_EXECUTE_INTR_EN_MASK 0x00000020L 236#define MMSCH_GPUIOV_CMD_CONTROL_1__VM_BUSY_INTR_EN_MASK 0x00000040L 237#define MMSCH_GPUIOV_CMD_CONTROL_1__FUNCTINO_ID_MASK 0x0000FF00L 238#define MMSCH_GPUIOV_CMD_CONTROL_1__NEXT_FUNCTINO_ID_MASK 0x00FF0000L 239//MMSCH_GPUIOV_CMD_STATUS_1 240#define MMSCH_GPUIOV_CMD_STATUS_1__CMD_STATUS__SHIFT 0x0 241#define MMSCH_GPUIOV_CMD_STATUS_1__CMD_STATUS_MASK 0x0000000FL 242//MMSCH_GPUIOV_VM_BUSY_STATUS_1 243#define MMSCH_GPUIOV_VM_BUSY_STATUS_1__BUSY__SHIFT 0x0 244#define MMSCH_GPUIOV_VM_BUSY_STATUS_1__BUSY_MASK 0xFFFFFFFFL 245//MMSCH_GPUIOV_ACTIVE_FCNS_1 246#define MMSCH_GPUIOV_ACTIVE_FCNS_1__ACTIVE_FCNS__SHIFT 0x0 247#define MMSCH_GPUIOV_ACTIVE_FCNS_1__ACTIVE_FCNS_MASK 0xFFFFFFFFL 248//MMSCH_GPUIOV_ACTIVE_FCN_ID_1 249#define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID__SHIFT 0x0 250#define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID_STATUS__SHIFT 0x8 251#define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID_MASK 0x000000FFL 252#define MMSCH_GPUIOV_ACTIVE_FCN_ID_1__ID_STATUS_MASK 0x00000F00L 253//MMSCH_GPUIOV_DW6_1 254#define MMSCH_GPUIOV_DW6_1__DATA__SHIFT 0x0 255#define MMSCH_GPUIOV_DW6_1__DATA_MASK 0xFFFFFFFFL 256//MMSCH_GPUIOV_DW7_1 257#define MMSCH_GPUIOV_DW7_1__DATA__SHIFT 0x0 258#define MMSCH_GPUIOV_DW7_1__DATA_MASK 0xFFFFFFFFL 259//MMSCH_GPUIOV_DW8_1 260#define MMSCH_GPUIOV_DW8_1__DATA__SHIFT 0x0 261#define MMSCH_GPUIOV_DW8_1__DATA_MASK 0xFFFFFFFFL 262//MMSCH_GPUIOV_CNTXT 263#define MMSCH_GPUIOV_CNTXT__CNTXT_SIZE__SHIFT 0x0 264#define MMSCH_GPUIOV_CNTXT__CNTXT_LOCATION__SHIFT 0x7 265#define MMSCH_GPUIOV_CNTXT__CNTXT_OFFSET__SHIFT 0xa 266#define MMSCH_GPUIOV_CNTXT__CNTXT_SIZE_MASK 0x0000007FL 267#define MMSCH_GPUIOV_CNTXT__CNTXT_LOCATION_MASK 0x00000080L 268#define MMSCH_GPUIOV_CNTXT__CNTXT_OFFSET_MASK 0xFFFFFC00L 269//MMSCH_SCRATCH_2 270#define MMSCH_SCRATCH_2__SCRATCH_2__SHIFT 0x0 271#define MMSCH_SCRATCH_2__SCRATCH_2_MASK 0xFFFFFFFFL 272//MMSCH_SCRATCH_3 273#define MMSCH_SCRATCH_3__SCRATCH_3__SHIFT 0x0 274#define MMSCH_SCRATCH_3__SCRATCH_3_MASK 0xFFFFFFFFL 275//MMSCH_SCRATCH_4 276#define MMSCH_SCRATCH_4__SCRATCH_4__SHIFT 0x0 277#define MMSCH_SCRATCH_4__SCRATCH_4_MASK 0xFFFFFFFFL 278//MMSCH_SCRATCH_5 279#define MMSCH_SCRATCH_5__SCRATCH_5__SHIFT 0x0 280#define MMSCH_SCRATCH_5__SCRATCH_5_MASK 0xFFFFFFFFL 281//MMSCH_SCRATCH_6 282#define MMSCH_SCRATCH_6__SCRATCH_6__SHIFT 0x0 283#define MMSCH_SCRATCH_6__SCRATCH_6_MASK 0xFFFFFFFFL 284//MMSCH_SCRATCH_7 285#define MMSCH_SCRATCH_7__SCRATCH_7__SHIFT 0x0 286#define MMSCH_SCRATCH_7__SCRATCH_7_MASK 0xFFFFFFFFL 287//MMSCH_VFID_FIFO_HEAD_0 288#define MMSCH_VFID_FIFO_HEAD_0__HEAD__SHIFT 0x0 289#define MMSCH_VFID_FIFO_HEAD_0__HEAD_MASK 0x0000003FL 290//MMSCH_VFID_FIFO_TAIL_0 291#define MMSCH_VFID_FIFO_TAIL_0__TAIL__SHIFT 0x0 292#define MMSCH_VFID_FIFO_TAIL_0__TAIL_MASK 0x0000003FL 293//MMSCH_VFID_FIFO_HEAD_1 294#define MMSCH_VFID_FIFO_HEAD_1__HEAD__SHIFT 0x0 295#define MMSCH_VFID_FIFO_HEAD_1__HEAD_MASK 0x0000003FL 296//MMSCH_VFID_FIFO_TAIL_1 297#define MMSCH_VFID_FIFO_TAIL_1__TAIL__SHIFT 0x0 298#define MMSCH_VFID_FIFO_TAIL_1__TAIL_MASK 0x0000003FL 299//MMSCH_NACK_STATUS 300#define MMSCH_NACK_STATUS__WR_NACK_STATUS__SHIFT 0x0 301#define MMSCH_NACK_STATUS__RD_NACK_STATUS__SHIFT 0x2 302#define MMSCH_NACK_STATUS__WR_NACK_STATUS_MASK 0x00000003L 303#define MMSCH_NACK_STATUS__RD_NACK_STATUS_MASK 0x0000000CL 304//MMSCH_VF_MAILBOX0_DATA 305#define MMSCH_VF_MAILBOX0_DATA__DATA__SHIFT 0x0 306#define MMSCH_VF_MAILBOX0_DATA__DATA_MASK 0xFFFFFFFFL 307//MMSCH_VF_MAILBOX1_DATA 308#define MMSCH_VF_MAILBOX1_DATA__DATA__SHIFT 0x0 309#define MMSCH_VF_MAILBOX1_DATA__DATA_MASK 0xFFFFFFFFL 310//MMSCH_GPUIOV_SCH_BLOCK_IP_0 311#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__ID__SHIFT 0x0 312#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__VERSION__SHIFT 0x4 313#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__SIZE__SHIFT 0x8 314#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__ID_MASK 0x0000000FL 315#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__VERSION_MASK 0x000000F0L 316#define MMSCH_GPUIOV_SCH_BLOCK_IP_0__SIZE_MASK 0x0000FF00L 317//MMSCH_GPUIOV_CMD_STATUS_IP_0 318#define MMSCH_GPUIOV_CMD_STATUS_IP_0__CMD_STATUS__SHIFT 0x0 319#define MMSCH_GPUIOV_CMD_STATUS_IP_0__CMD_STATUS_MASK 0x0000000FL 320//MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0 321#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID__SHIFT 0x0 322#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID_STATUS__SHIFT 0x8 323#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID_MASK 0x000000FFL 324#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_0__ID_STATUS_MASK 0x00000F00L 325//MMSCH_GPUIOV_SCH_BLOCK_IP_1 326#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__ID__SHIFT 0x0 327#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__VERSION__SHIFT 0x4 328#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__SIZE__SHIFT 0x8 329#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__ID_MASK 0x0000000FL 330#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__VERSION_MASK 0x000000F0L 331#define MMSCH_GPUIOV_SCH_BLOCK_IP_1__SIZE_MASK 0x0000FF00L 332//MMSCH_GPUIOV_CMD_STATUS_IP_1 333#define MMSCH_GPUIOV_CMD_STATUS_IP_1__CMD_STATUS__SHIFT 0x0 334#define MMSCH_GPUIOV_CMD_STATUS_IP_1__CMD_STATUS_MASK 0x0000000FL 335//MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1 336#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID__SHIFT 0x0 337#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID_STATUS__SHIFT 0x8 338#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID_MASK 0x000000FFL 339#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_1__ID_STATUS_MASK 0x00000F00L 340//MMSCH_GPUIOV_CNTXT_IP 341#define MMSCH_GPUIOV_CNTXT_IP__CNTXT_SIZE__SHIFT 0x0 342#define MMSCH_GPUIOV_CNTXT_IP__CNTXT_LOCATION__SHIFT 0x7 343#define MMSCH_GPUIOV_CNTXT_IP__CNTXT_SIZE_MASK 0x0000007FL 344#define MMSCH_GPUIOV_CNTXT_IP__CNTXT_LOCATION_MASK 0x00000080L 345//MMSCH_GPUIOV_SCH_BLOCK_2 346#define MMSCH_GPUIOV_SCH_BLOCK_2__ID__SHIFT 0x0 347#define MMSCH_GPUIOV_SCH_BLOCK_2__VERSION__SHIFT 0x4 348#define MMSCH_GPUIOV_SCH_BLOCK_2__SIZE__SHIFT 0x8 349#define MMSCH_GPUIOV_SCH_BLOCK_2__ID_MASK 0x0000000FL 350#define MMSCH_GPUIOV_SCH_BLOCK_2__VERSION_MASK 0x000000F0L 351#define MMSCH_GPUIOV_SCH_BLOCK_2__SIZE_MASK 0x0000FF00L 352//MMSCH_GPUIOV_CMD_CONTROL_2 353#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_TYPE__SHIFT 0x0 354#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE__SHIFT 0x4 355#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_INTR_EN__SHIFT 0x5 356#define MMSCH_GPUIOV_CMD_CONTROL_2__VM_BUSY_INTR_EN__SHIFT 0x6 357#define MMSCH_GPUIOV_CMD_CONTROL_2__FUNCTINO_ID__SHIFT 0x8 358#define MMSCH_GPUIOV_CMD_CONTROL_2__NEXT_FUNCTINO_ID__SHIFT 0x10 359#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_TYPE_MASK 0x0000000FL 360#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_MASK 0x00000010L 361#define MMSCH_GPUIOV_CMD_CONTROL_2__CMD_EXECUTE_INTR_EN_MASK 0x00000020L 362#define MMSCH_GPUIOV_CMD_CONTROL_2__VM_BUSY_INTR_EN_MASK 0x00000040L 363#define MMSCH_GPUIOV_CMD_CONTROL_2__FUNCTINO_ID_MASK 0x0000FF00L 364#define MMSCH_GPUIOV_CMD_CONTROL_2__NEXT_FUNCTINO_ID_MASK 0x00FF0000L 365//MMSCH_GPUIOV_CMD_STATUS_2 366#define MMSCH_GPUIOV_CMD_STATUS_2__CMD_STATUS__SHIFT 0x0 367#define MMSCH_GPUIOV_CMD_STATUS_2__CMD_STATUS_MASK 0x0000000FL 368//MMSCH_GPUIOV_VM_BUSY_STATUS_2 369#define MMSCH_GPUIOV_VM_BUSY_STATUS_2__BUSY__SHIFT 0x0 370#define MMSCH_GPUIOV_VM_BUSY_STATUS_2__BUSY_MASK 0xFFFFFFFFL 371//MMSCH_GPUIOV_ACTIVE_FCNS_2 372#define MMSCH_GPUIOV_ACTIVE_FCNS_2__ACTIVE_FCNS__SHIFT 0x0 373#define MMSCH_GPUIOV_ACTIVE_FCNS_2__ACTIVE_FCNS_MASK 0xFFFFFFFFL 374//MMSCH_GPUIOV_ACTIVE_FCN_ID_2 375#define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID__SHIFT 0x0 376#define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID_STATUS__SHIFT 0x8 377#define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID_MASK 0x000000FFL 378#define MMSCH_GPUIOV_ACTIVE_FCN_ID_2__ID_STATUS_MASK 0x00000F00L 379//MMSCH_GPUIOV_DW6_2 380#define MMSCH_GPUIOV_DW6_2__DATA__SHIFT 0x0 381#define MMSCH_GPUIOV_DW6_2__DATA_MASK 0xFFFFFFFFL 382//MMSCH_GPUIOV_DW7_2 383#define MMSCH_GPUIOV_DW7_2__DATA__SHIFT 0x0 384#define MMSCH_GPUIOV_DW7_2__DATA_MASK 0xFFFFFFFFL 385//MMSCH_GPUIOV_DW8_2 386#define MMSCH_GPUIOV_DW8_2__DATA__SHIFT 0x0 387#define MMSCH_GPUIOV_DW8_2__DATA_MASK 0xFFFFFFFFL 388//MMSCH_GPUIOV_SCH_BLOCK_IP_2 389#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__ID__SHIFT 0x0 390#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__VERSION__SHIFT 0x4 391#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__SIZE__SHIFT 0x8 392#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__ID_MASK 0x0000000FL 393#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__VERSION_MASK 0x000000F0L 394#define MMSCH_GPUIOV_SCH_BLOCK_IP_2__SIZE_MASK 0x0000FF00L 395//MMSCH_GPUIOV_CMD_STATUS_IP_2 396#define MMSCH_GPUIOV_CMD_STATUS_IP_2__CMD_STATUS__SHIFT 0x0 397#define MMSCH_GPUIOV_CMD_STATUS_IP_2__CMD_STATUS_MASK 0x0000000FL 398//MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2 399#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID__SHIFT 0x0 400#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID_STATUS__SHIFT 0x8 401#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID_MASK 0x000000FFL 402#define MMSCH_GPUIOV_ACTIVE_FCN_ID_IP_2__ID_STATUS_MASK 0x00000F00L 403//MMSCH_VFID_FIFO_HEAD_2 404#define MMSCH_VFID_FIFO_HEAD_2__HEAD__SHIFT 0x0 405#define MMSCH_VFID_FIFO_HEAD_2__HEAD_MASK 0x0000003FL 406//MMSCH_VFID_FIFO_TAIL_2 407#define MMSCH_VFID_FIFO_TAIL_2__TAIL__SHIFT 0x0 408#define MMSCH_VFID_FIFO_TAIL_2__TAIL_MASK 0x0000003FL 409//MMSCH_VM_BUSY_STATUS_0 410#define MMSCH_VM_BUSY_STATUS_0__BUSY__SHIFT 0x0 411#define MMSCH_VM_BUSY_STATUS_0__BUSY_MASK 0xFFFFFFFFL 412//MMSCH_VM_BUSY_STATUS_1 413#define MMSCH_VM_BUSY_STATUS_1__BUSY__SHIFT 0x0 414#define MMSCH_VM_BUSY_STATUS_1__BUSY_MASK 0xFFFFFFFFL 415//MMSCH_VM_BUSY_STATUS_2 416#define MMSCH_VM_BUSY_STATUS_2__BUSY__SHIFT 0x0 417#define MMSCH_VM_BUSY_STATUS_2__BUSY_MASK 0xFFFFFFFFL 418 419 420// addressBlock: uvd0_jpegnpdec 421//UVD_JPEG_CNTL 422#define UVD_JPEG_CNTL__REQUEST_EN__SHIFT 0x1 423#define UVD_JPEG_CNTL__ERR_RST_EN__SHIFT 0x2 424#define UVD_JPEG_CNTL__HUFF_SPEED_EN__SHIFT 0x3 425#define UVD_JPEG_CNTL__HUFF_SPEED_STATUS__SHIFT 0x4 426#define UVD_JPEG_CNTL__DBG_MUX_SEL__SHIFT 0x8 427#define UVD_JPEG_CNTL__REQUEST_EN_MASK 0x00000002L 428#define UVD_JPEG_CNTL__ERR_RST_EN_MASK 0x00000004L 429#define UVD_JPEG_CNTL__HUFF_SPEED_EN_MASK 0x00000008L 430#define UVD_JPEG_CNTL__HUFF_SPEED_STATUS_MASK 0x00000010L 431#define UVD_JPEG_CNTL__DBG_MUX_SEL_MASK 0x00007F00L 432//UVD_JPEG_RB_BASE 433#define UVD_JPEG_RB_BASE__RB_BYTE_OFF__SHIFT 0x0 434#define UVD_JPEG_RB_BASE__RB_BASE__SHIFT 0x6 435#define UVD_JPEG_RB_BASE__RB_BYTE_OFF_MASK 0x0000003FL 436#define UVD_JPEG_RB_BASE__RB_BASE_MASK 0xFFFFFFC0L 437//UVD_JPEG_RB_WPTR 438#define UVD_JPEG_RB_WPTR__RB_WPTR__SHIFT 0x4 439#define UVD_JPEG_RB_WPTR__RB_WPTR_MASK 0x3FFFFFF0L 440//UVD_JPEG_RB_RPTR 441#define UVD_JPEG_RB_RPTR__RB_RPTR__SHIFT 0x4 442#define UVD_JPEG_RB_RPTR__RB_RPTR_MASK 0x3FFFFFF0L 443//UVD_JPEG_RB_SIZE 444#define UVD_JPEG_RB_SIZE__RB_SIZE__SHIFT 0x4 445#define UVD_JPEG_RB_SIZE__RB_SIZE_MASK 0x3FFFFFF0L 446//UVD_JPEG_DEC_SCRATCH0 447#define UVD_JPEG_DEC_SCRATCH0__SCRATCH0__SHIFT 0x0 448#define UVD_JPEG_DEC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL 449//UVD_JPEG_INT_EN 450#define UVD_JPEG_INT_EN__OUTBUF_WPTR_INC_EN__SHIFT 0x0 451#define UVD_JPEG_INT_EN__JOB_AVAIL_EN__SHIFT 0x1 452#define UVD_JPEG_INT_EN__FENCE_VAL_EN__SHIFT 0x2 453#define UVD_JPEG_INT_EN__FIFO_OVERFLOW_ERR_EN__SHIFT 0x6 454#define UVD_JPEG_INT_EN__BLK_CNT_OUT_OF_SYNC_ERR_EN__SHIFT 0x7 455#define UVD_JPEG_INT_EN__EOI_ERR_EN__SHIFT 0x8 456#define UVD_JPEG_INT_EN__HFM_ERR_EN__SHIFT 0x9 457#define UVD_JPEG_INT_EN__RST_ERR_EN__SHIFT 0xa 458#define UVD_JPEG_INT_EN__ECS_MK_ERR_EN__SHIFT 0xb 459#define UVD_JPEG_INT_EN__TIMEOUT_ERR_EN__SHIFT 0xc 460#define UVD_JPEG_INT_EN__MARKER_ERR_EN__SHIFT 0xd 461#define UVD_JPEG_INT_EN__FMT_ERR_EN__SHIFT 0xe 462#define UVD_JPEG_INT_EN__PROFILE_ERR_EN__SHIFT 0xf 463#define UVD_JPEG_INT_EN__OUTBUF_WPTR_INC_EN_MASK 0x00000001L 464#define UVD_JPEG_INT_EN__JOB_AVAIL_EN_MASK 0x00000002L 465#define UVD_JPEG_INT_EN__FENCE_VAL_EN_MASK 0x00000004L 466#define UVD_JPEG_INT_EN__FIFO_OVERFLOW_ERR_EN_MASK 0x00000040L 467#define UVD_JPEG_INT_EN__BLK_CNT_OUT_OF_SYNC_ERR_EN_MASK 0x00000080L 468#define UVD_JPEG_INT_EN__EOI_ERR_EN_MASK 0x00000100L 469#define UVD_JPEG_INT_EN__HFM_ERR_EN_MASK 0x00000200L 470#define UVD_JPEG_INT_EN__RST_ERR_EN_MASK 0x00000400L 471#define UVD_JPEG_INT_EN__ECS_MK_ERR_EN_MASK 0x00000800L 472#define UVD_JPEG_INT_EN__TIMEOUT_ERR_EN_MASK 0x00001000L 473#define UVD_JPEG_INT_EN__MARKER_ERR_EN_MASK 0x00002000L 474#define UVD_JPEG_INT_EN__FMT_ERR_EN_MASK 0x00004000L 475#define UVD_JPEG_INT_EN__PROFILE_ERR_EN_MASK 0x00008000L 476//UVD_JPEG_INT_STAT 477#define UVD_JPEG_INT_STAT__OUTBUF_WPTR_INC_INT__SHIFT 0x0 478#define UVD_JPEG_INT_STAT__JOB_AVAIL_INT__SHIFT 0x1 479#define UVD_JPEG_INT_STAT__FENCE_VAL_INT__SHIFT 0x2 480#define UVD_JPEG_INT_STAT__FIFO_OVERFLOW_ERR_INT__SHIFT 0x6 481#define UVD_JPEG_INT_STAT__BLK_CNT_OUT_OF_SYNC_ERR_INT__SHIFT 0x7 482#define UVD_JPEG_INT_STAT__EOI_ERR_INT__SHIFT 0x8 483#define UVD_JPEG_INT_STAT__HFM_ERR_INT__SHIFT 0x9 484#define UVD_JPEG_INT_STAT__RST_ERR_INT__SHIFT 0xa 485#define UVD_JPEG_INT_STAT__ECS_MK_ERR_INT__SHIFT 0xb 486#define UVD_JPEG_INT_STAT__TIMEOUT_ERR_INT__SHIFT 0xc 487#define UVD_JPEG_INT_STAT__MARKER_ERR_INT__SHIFT 0xd 488#define UVD_JPEG_INT_STAT__FMT_ERR_INT__SHIFT 0xe 489#define UVD_JPEG_INT_STAT__PROFILE_ERR_INT__SHIFT 0xf 490#define UVD_JPEG_INT_STAT__OUTBUF_WPTR_INC_INT_MASK 0x00000001L 491#define UVD_JPEG_INT_STAT__JOB_AVAIL_INT_MASK 0x00000002L 492#define UVD_JPEG_INT_STAT__FENCE_VAL_INT_MASK 0x00000004L 493#define UVD_JPEG_INT_STAT__FIFO_OVERFLOW_ERR_INT_MASK 0x00000040L 494#define UVD_JPEG_INT_STAT__BLK_CNT_OUT_OF_SYNC_ERR_INT_MASK 0x00000080L 495#define UVD_JPEG_INT_STAT__EOI_ERR_INT_MASK 0x00000100L 496#define UVD_JPEG_INT_STAT__HFM_ERR_INT_MASK 0x00000200L 497#define UVD_JPEG_INT_STAT__RST_ERR_INT_MASK 0x00000400L 498#define UVD_JPEG_INT_STAT__ECS_MK_ERR_INT_MASK 0x00000800L 499#define UVD_JPEG_INT_STAT__TIMEOUT_ERR_INT_MASK 0x00001000L 500#define UVD_JPEG_INT_STAT__MARKER_ERR_INT_MASK 0x00002000L 501#define UVD_JPEG_INT_STAT__FMT_ERR_INT_MASK 0x00004000L 502#define UVD_JPEG_INT_STAT__PROFILE_ERR_INT_MASK 0x00008000L 503//UVD_JPEG_PITCH 504#define UVD_JPEG_PITCH__PITCH__SHIFT 0x0 505#define UVD_JPEG_PITCH__PITCH_MASK 0xFFFFFFFFL 506//UVD_JPEG_UV_PITCH 507#define UVD_JPEG_UV_PITCH__UV_PITCH__SHIFT 0x0 508#define UVD_JPEG_UV_PITCH__UV_PITCH_MASK 0xFFFFFFFFL 509//JPEG_DEC_Y_GFX8_TILING_SURFACE 510#define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_WIDTH__SHIFT 0x0 511#define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_HEIGHT__SHIFT 0x2 512#define JPEG_DEC_Y_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT__SHIFT 0x4 513#define JPEG_DEC_Y_GFX8_TILING_SURFACE__NUM_BANKS__SHIFT 0x6 514#define JPEG_DEC_Y_GFX8_TILING_SURFACE__PIPE_CONFIG__SHIFT 0x8 515#define JPEG_DEC_Y_GFX8_TILING_SURFACE__TILE_SPLIT__SHIFT 0xd 516#define JPEG_DEC_Y_GFX8_TILING_SURFACE__ARRAY_MODE__SHIFT 0x10 517#define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_WIDTH_MASK 0x00000003L 518#define JPEG_DEC_Y_GFX8_TILING_SURFACE__BANK_HEIGHT_MASK 0x0000000CL 519#define JPEG_DEC_Y_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT_MASK 0x00000030L 520#define JPEG_DEC_Y_GFX8_TILING_SURFACE__NUM_BANKS_MASK 0x000000C0L 521#define JPEG_DEC_Y_GFX8_TILING_SURFACE__PIPE_CONFIG_MASK 0x00001F00L 522#define JPEG_DEC_Y_GFX8_TILING_SURFACE__TILE_SPLIT_MASK 0x0000E000L 523#define JPEG_DEC_Y_GFX8_TILING_SURFACE__ARRAY_MODE_MASK 0x000F0000L 524//JPEG_DEC_UV_GFX8_TILING_SURFACE 525#define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_WIDTH__SHIFT 0x0 526#define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_HEIGHT__SHIFT 0x2 527#define JPEG_DEC_UV_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT__SHIFT 0x4 528#define JPEG_DEC_UV_GFX8_TILING_SURFACE__NUM_BANKS__SHIFT 0x6 529#define JPEG_DEC_UV_GFX8_TILING_SURFACE__PIPE_CONFIG__SHIFT 0x8 530#define JPEG_DEC_UV_GFX8_TILING_SURFACE__TILE_SPLIT__SHIFT 0xd 531#define JPEG_DEC_UV_GFX8_TILING_SURFACE__ARRAY_MODE__SHIFT 0x10 532#define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_WIDTH_MASK 0x00000003L 533#define JPEG_DEC_UV_GFX8_TILING_SURFACE__BANK_HEIGHT_MASK 0x0000000CL 534#define JPEG_DEC_UV_GFX8_TILING_SURFACE__MACRO_TILE_ASPECT_MASK 0x00000030L 535#define JPEG_DEC_UV_GFX8_TILING_SURFACE__NUM_BANKS_MASK 0x000000C0L 536#define JPEG_DEC_UV_GFX8_TILING_SURFACE__PIPE_CONFIG_MASK 0x00001F00L 537#define JPEG_DEC_UV_GFX8_TILING_SURFACE__TILE_SPLIT_MASK 0x0000E000L 538#define JPEG_DEC_UV_GFX8_TILING_SURFACE__ARRAY_MODE_MASK 0x000F0000L 539//JPEG_DEC_GFX8_ADDR_CONFIG 540#define JPEG_DEC_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 541#define JPEG_DEC_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L 542//JPEG_DEC_Y_GFX10_TILING_SURFACE 543#define JPEG_DEC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0 544#define JPEG_DEC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL 545//JPEG_DEC_UV_GFX10_TILING_SURFACE 546#define JPEG_DEC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0 547#define JPEG_DEC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL 548//JPEG_DEC_GFX10_ADDR_CONFIG 549#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 550#define JPEG_DEC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 551#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 552#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 553#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 554#define JPEG_DEC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 555#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 556#define JPEG_DEC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 557//JPEG_DEC_ADDR_MODE 558#define JPEG_DEC_ADDR_MODE__ADDR_MODE_Y__SHIFT 0x0 559#define JPEG_DEC_ADDR_MODE__ADDR_MODE_UV__SHIFT 0x2 560#define JPEG_DEC_ADDR_MODE__ADDR_LIB_SEL__SHIFT 0xc 561#define JPEG_DEC_ADDR_MODE__ADDR_MODE_Y_MASK 0x00000003L 562#define JPEG_DEC_ADDR_MODE__ADDR_MODE_UV_MASK 0x0000000CL 563#define JPEG_DEC_ADDR_MODE__ADDR_LIB_SEL_MASK 0x00007000L 564//UVD_JPEG_OUTPUT_XY 565//UVD_JPEG_GPCOM_CMD 566#define UVD_JPEG_GPCOM_CMD__CMD__SHIFT 0x1 567#define UVD_JPEG_GPCOM_CMD__CMD_MASK 0x0000000EL 568//UVD_JPEG_GPCOM_DATA0 569#define UVD_JPEG_GPCOM_DATA0__DATA0__SHIFT 0x0 570#define UVD_JPEG_GPCOM_DATA0__DATA0_MASK 0xFFFFFFFFL 571//UVD_JPEG_GPCOM_DATA1 572#define UVD_JPEG_GPCOM_DATA1__DATA1__SHIFT 0x0 573#define UVD_JPEG_GPCOM_DATA1__DATA1_MASK 0xFFFFFFFFL 574//UVD_JPEG_SCRATCH1 575#define UVD_JPEG_SCRATCH1__SCRATCH1__SHIFT 0x0 576#define UVD_JPEG_SCRATCH1__SCRATCH1_MASK 0xFFFFFFFFL 577//UVD_JPEG_DEC_SOFT_RST 578#define UVD_JPEG_DEC_SOFT_RST__SOFT_RESET__SHIFT 0x0 579#define UVD_JPEG_DEC_SOFT_RST__RESET_STATUS__SHIFT 0x10 580#define UVD_JPEG_DEC_SOFT_RST__SOFT_RESET_MASK 0x00000001L 581#define UVD_JPEG_DEC_SOFT_RST__RESET_STATUS_MASK 0x00010000L 582 583 584// addressBlock: uvd0_uvd_jpeg_enc_dec 585//UVD_JPEG_ENC_INT_EN 586#define UVD_JPEG_ENC_INT_EN__HUFF_JOB_DONE_INT_EN__SHIFT 0x0 587#define UVD_JPEG_ENC_INT_EN__SCLR_JOB_DONE_INT_EN__SHIFT 0x1 588#define UVD_JPEG_ENC_INT_EN__HUFF_ERROR_INT_EN__SHIFT 0x2 589#define UVD_JPEG_ENC_INT_EN__SCLR_ERROR_INT_EN__SHIFT 0x3 590#define UVD_JPEG_ENC_INT_EN__QTBL_ERROR_INT_EN__SHIFT 0x4 591#define UVD_JPEG_ENC_INT_EN__PIC_SIZE_ERROR_INT_EN__SHIFT 0x5 592#define UVD_JPEG_ENC_INT_EN__FENCE_VAL_INT_EN__SHIFT 0x6 593#define UVD_JPEG_ENC_INT_EN__HUFF_JOB_DONE_INT_EN_MASK 0x00000001L 594#define UVD_JPEG_ENC_INT_EN__SCLR_JOB_DONE_INT_EN_MASK 0x00000002L 595#define UVD_JPEG_ENC_INT_EN__HUFF_ERROR_INT_EN_MASK 0x00000004L 596#define UVD_JPEG_ENC_INT_EN__SCLR_ERROR_INT_EN_MASK 0x00000008L 597#define UVD_JPEG_ENC_INT_EN__QTBL_ERROR_INT_EN_MASK 0x00000010L 598#define UVD_JPEG_ENC_INT_EN__PIC_SIZE_ERROR_INT_EN_MASK 0x00000020L 599#define UVD_JPEG_ENC_INT_EN__FENCE_VAL_INT_EN_MASK 0x00000040L 600//UVD_JPEG_ENC_INT_STATUS 601#define UVD_JPEG_ENC_INT_STATUS__HUFF_JOB_DONE_STATUS__SHIFT 0x0 602#define UVD_JPEG_ENC_INT_STATUS__SCLR_JOB_DONE_STATUS__SHIFT 0x1 603#define UVD_JPEG_ENC_INT_STATUS__HUFF_ERROR_STATUS__SHIFT 0x2 604#define UVD_JPEG_ENC_INT_STATUS__SCLR_ERROR_STATUS__SHIFT 0x3 605#define UVD_JPEG_ENC_INT_STATUS__QTBL_ERROR_STATUS__SHIFT 0x4 606#define UVD_JPEG_ENC_INT_STATUS__PIC_SIZE_ERROR_STATUS__SHIFT 0x5 607#define UVD_JPEG_ENC_INT_STATUS__FENCE_VAL_STATUS__SHIFT 0x6 608#define UVD_JPEG_ENC_INT_STATUS__HUFF_JOB_DONE_STATUS_MASK 0x00000001L 609#define UVD_JPEG_ENC_INT_STATUS__SCLR_JOB_DONE_STATUS_MASK 0x00000002L 610#define UVD_JPEG_ENC_INT_STATUS__HUFF_ERROR_STATUS_MASK 0x00000004L 611#define UVD_JPEG_ENC_INT_STATUS__SCLR_ERROR_STATUS_MASK 0x00000008L 612#define UVD_JPEG_ENC_INT_STATUS__QTBL_ERROR_STATUS_MASK 0x00000010L 613#define UVD_JPEG_ENC_INT_STATUS__PIC_SIZE_ERROR_STATUS_MASK 0x00000020L 614#define UVD_JPEG_ENC_INT_STATUS__FENCE_VAL_STATUS_MASK 0x00000040L 615//UVD_JPEG_ENC_ENGINE_CNTL 616#define UVD_JPEG_ENC_ENGINE_CNTL__HUFF_WR_COMB_DIS__SHIFT 0x0 617#define UVD_JPEG_ENC_ENGINE_CNTL__DISTINCT_CHROMA_QUANT_TABLES__SHIFT 0x1 618#define UVD_JPEG_ENC_ENGINE_CNTL__SCALAR_EN__SHIFT 0x2 619#define UVD_JPEG_ENC_ENGINE_CNTL__ENCODE_EN__SHIFT 0x3 620#define UVD_JPEG_ENC_ENGINE_CNTL__CMP_NEEDED__SHIFT 0x4 621#define UVD_JPEG_ENC_ENGINE_CNTL__ECS_RESTRICT_32B_EN__SHIFT 0x9 622#define UVD_JPEG_ENC_ENGINE_CNTL__HUFF_WR_COMB_DIS_MASK 0x00000001L 623#define UVD_JPEG_ENC_ENGINE_CNTL__DISTINCT_CHROMA_QUANT_TABLES_MASK 0x00000002L 624#define UVD_JPEG_ENC_ENGINE_CNTL__SCALAR_EN_MASK 0x00000004L 625#define UVD_JPEG_ENC_ENGINE_CNTL__ENCODE_EN_MASK 0x00000008L 626#define UVD_JPEG_ENC_ENGINE_CNTL__CMP_NEEDED_MASK 0x00000010L 627#define UVD_JPEG_ENC_ENGINE_CNTL__ECS_RESTRICT_32B_EN_MASK 0x00000200L 628//UVD_JPEG_ENC_SCRATCH1 629#define UVD_JPEG_ENC_SCRATCH1__SCRATCH1__SHIFT 0x0 630#define UVD_JPEG_ENC_SCRATCH1__SCRATCH1_MASK 0xFFFFFFFFL 631 632 633// addressBlock: uvd0_uvd_jpeg_enc_sclk_dec 634//UVD_JPEG_ENC_STATUS 635#define UVD_JPEG_ENC_STATUS__PEL_FETCH_IDLE__SHIFT 0x0 636#define UVD_JPEG_ENC_STATUS__HUFF_CORE_IDLE__SHIFT 0x1 637#define UVD_JPEG_ENC_STATUS__FDCT_IDLE__SHIFT 0x2 638#define UVD_JPEG_ENC_STATUS__SCALAR_IDLE__SHIFT 0x3 639#define UVD_JPEG_ENC_STATUS__PEL_FETCH_IDLE_MASK 0x00000001L 640#define UVD_JPEG_ENC_STATUS__HUFF_CORE_IDLE_MASK 0x00000002L 641#define UVD_JPEG_ENC_STATUS__FDCT_IDLE_MASK 0x00000004L 642#define UVD_JPEG_ENC_STATUS__SCALAR_IDLE_MASK 0x00000008L 643//UVD_JPEG_ENC_PITCH 644#define UVD_JPEG_ENC_PITCH__PITCH_Y__SHIFT 0x0 645#define UVD_JPEG_ENC_PITCH__PITCH_UV__SHIFT 0x10 646#define UVD_JPEG_ENC_PITCH__PITCH_Y_MASK 0x00000FFFL 647#define UVD_JPEG_ENC_PITCH__PITCH_UV_MASK 0x0FFF0000L 648//UVD_JPEG_ENC_LUMA_BASE 649#define UVD_JPEG_ENC_LUMA_BASE__LUMA_BASE__SHIFT 0x0 650#define UVD_JPEG_ENC_LUMA_BASE__LUMA_BASE_MASK 0xFFFFFFFFL 651//UVD_JPEG_ENC_CHROMAU_BASE 652#define UVD_JPEG_ENC_CHROMAU_BASE__CHROMAU_BASE__SHIFT 0x0 653#define UVD_JPEG_ENC_CHROMAU_BASE__CHROMAU_BASE_MASK 0xFFFFFFFFL 654//UVD_JPEG_ENC_CHROMAV_BASE 655#define UVD_JPEG_ENC_CHROMAV_BASE__CHROMAV_BASE__SHIFT 0x0 656#define UVD_JPEG_ENC_CHROMAV_BASE__CHROMAV_BASE_MASK 0xFFFFFFFFL 657//JPEG_ENC_Y_GFX10_TILING_SURFACE 658#define JPEG_ENC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0 659#define JPEG_ENC_Y_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL 660//JPEG_ENC_UV_GFX10_TILING_SURFACE 661#define JPEG_ENC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE__SHIFT 0x0 662#define JPEG_ENC_UV_GFX10_TILING_SURFACE__SWIZZLE_MODE_MASK 0x0000001FL 663//JPEG_ENC_GFX10_ADDR_CONFIG 664#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 665#define JPEG_ENC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 666#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 667#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 668#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 669#define JPEG_ENC_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 670#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 671#define JPEG_ENC_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 672//JPEG_ENC_ADDR_MODE 673#define JPEG_ENC_ADDR_MODE__ADDR_MODE_Y__SHIFT 0x0 674#define JPEG_ENC_ADDR_MODE__ADDR_MODE_UV__SHIFT 0x2 675#define JPEG_ENC_ADDR_MODE__ADDR_LIB_SEL__SHIFT 0xc 676#define JPEG_ENC_ADDR_MODE__ADDR_MODE_Y_MASK 0x00000003L 677#define JPEG_ENC_ADDR_MODE__ADDR_MODE_UV_MASK 0x0000000CL 678#define JPEG_ENC_ADDR_MODE__ADDR_LIB_SEL_MASK 0x00007000L 679//UVD_JPEG_ENC_GPCOM_CMD 680#define UVD_JPEG_ENC_GPCOM_CMD__CMD__SHIFT 0x1 681#define UVD_JPEG_ENC_GPCOM_CMD__CMD_MASK 0x0000000EL 682//UVD_JPEG_ENC_GPCOM_DATA0 683#define UVD_JPEG_ENC_GPCOM_DATA0__DATA0__SHIFT 0x0 684#define UVD_JPEG_ENC_GPCOM_DATA0__DATA0_MASK 0xFFFFFFFFL 685//UVD_JPEG_ENC_GPCOM_DATA1 686#define UVD_JPEG_ENC_GPCOM_DATA1__DATA1__SHIFT 0x0 687#define UVD_JPEG_ENC_GPCOM_DATA1__DATA1_MASK 0xFFFFFFFFL 688//UVD_JPEG_ENC_CGC_CNTL 689#define UVD_JPEG_ENC_CGC_CNTL__CGC_EN__SHIFT 0x0 690#define UVD_JPEG_ENC_CGC_CNTL__CGC_EN_MASK 0x00000001L 691//UVD_JPEG_ENC_SCRATCH0 692#define UVD_JPEG_ENC_SCRATCH0__SCRATCH0__SHIFT 0x0 693#define UVD_JPEG_ENC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL 694//UVD_JPEG_ENC_SOFT_RST 695#define UVD_JPEG_ENC_SOFT_RST__SOFT_RST__SHIFT 0x0 696#define UVD_JPEG_ENC_SOFT_RST__RESET_STATUS__SHIFT 0x10 697#define UVD_JPEG_ENC_SOFT_RST__SOFT_RST_MASK 0x00000001L 698#define UVD_JPEG_ENC_SOFT_RST__RESET_STATUS_MASK 0x00010000L 699 700 701// addressBlock: uvd0_uvd_jrbc_dec 702//UVD_JRBC_RB_WPTR 703#define UVD_JRBC_RB_WPTR__RB_WPTR__SHIFT 0x4 704#define UVD_JRBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 705//UVD_JRBC_RB_CNTL 706#define UVD_JRBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x0 707#define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1 708#define UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x4 709#define UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK 0x00000001L 710#define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L 711#define UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK 0x0007FFF0L 712//UVD_JRBC_IB_SIZE 713#define UVD_JRBC_IB_SIZE__IB_SIZE__SHIFT 0x4 714#define UVD_JRBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L 715//UVD_JRBC_URGENT_CNTL 716#define UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0 717#define UVD_JRBC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L 718//UVD_JRBC_RB_REF_DATA 719#define UVD_JRBC_RB_REF_DATA__REF_DATA__SHIFT 0x0 720#define UVD_JRBC_RB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 721//UVD_JRBC_RB_COND_RD_TIMER 722#define UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 723#define UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 724#define UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 725#define UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 726#define UVD_JRBC_RB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 727#define UVD_JRBC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 728#define UVD_JRBC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 729#define UVD_JRBC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 730//UVD_JRBC_SOFT_RESET 731#define UVD_JRBC_SOFT_RESET__RESET__SHIFT 0x0 732#define UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT 0x11 733#define UVD_JRBC_SOFT_RESET__RESET_MASK 0x00000001L 734#define UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS_MASK 0x00020000L 735//UVD_JRBC_STATUS 736#define UVD_JRBC_STATUS__RB_JOB_DONE__SHIFT 0x0 737#define UVD_JRBC_STATUS__IB_JOB_DONE__SHIFT 0x1 738#define UVD_JRBC_STATUS__RB_ILLEGAL_CMD__SHIFT 0x2 739#define UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT 0x3 740#define UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT 0x4 741#define UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT 0x5 742#define UVD_JRBC_STATUS__IB_ILLEGAL_CMD__SHIFT 0x6 743#define UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT 0x7 744#define UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT 0x8 745#define UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT 0x9 746#define UVD_JRBC_STATUS__RB_TRAP_STATUS__SHIFT 0xa 747#define UVD_JRBC_STATUS__PREEMPT_STATUS__SHIFT 0xb 748#define UVD_JRBC_STATUS__IB_TRAP_STATUS__SHIFT 0xc 749#define UVD_JRBC_STATUS__INT_EN__SHIFT 0x10 750#define UVD_JRBC_STATUS__INT_ACK__SHIFT 0x11 751#define UVD_JRBC_STATUS__RB_JOB_DONE_MASK 0x00000001L 752#define UVD_JRBC_STATUS__IB_JOB_DONE_MASK 0x00000002L 753#define UVD_JRBC_STATUS__RB_ILLEGAL_CMD_MASK 0x00000004L 754#define UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK 0x00000008L 755#define UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT_MASK 0x00000010L 756#define UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT_MASK 0x00000020L 757#define UVD_JRBC_STATUS__IB_ILLEGAL_CMD_MASK 0x00000040L 758#define UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK 0x00000080L 759#define UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT_MASK 0x00000100L 760#define UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT_MASK 0x00000200L 761#define UVD_JRBC_STATUS__RB_TRAP_STATUS_MASK 0x00000400L 762#define UVD_JRBC_STATUS__PREEMPT_STATUS_MASK 0x00000800L 763#define UVD_JRBC_STATUS__IB_TRAP_STATUS_MASK 0x00001000L 764#define UVD_JRBC_STATUS__INT_EN_MASK 0x00010000L 765#define UVD_JRBC_STATUS__INT_ACK_MASK 0x00020000L 766//UVD_JRBC_RB_RPTR 767#define UVD_JRBC_RB_RPTR__RB_RPTR__SHIFT 0x4 768#define UVD_JRBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 769//UVD_JRBC_RB_BUF_STATUS 770#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0 771#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10 772#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x18 773#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_VALID_MASK 0x0000FFFFL 774#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x000F0000L 775#define UVD_JRBC_RB_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x03000000L 776//UVD_JRBC_IB_BUF_STATUS 777#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID__SHIFT 0x0 778#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x10 779#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x18 780#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FFFFL 781#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x000F0000L 782#define UVD_JRBC_IB_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x03000000L 783//UVD_JRBC_IB_SIZE_UPDATE 784#define UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4 785#define UVD_JRBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L 786//UVD_JRBC_IB_COND_RD_TIMER 787#define UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 788#define UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 789#define UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 790#define UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 791#define UVD_JRBC_IB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 792#define UVD_JRBC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 793#define UVD_JRBC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 794#define UVD_JRBC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 795//UVD_JRBC_IB_REF_DATA 796#define UVD_JRBC_IB_REF_DATA__REF_DATA__SHIFT 0x0 797#define UVD_JRBC_IB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 798//UVD_JPEG_PREEMPT_CMD 799#define UVD_JPEG_PREEMPT_CMD__PREEMPT_EN__SHIFT 0x0 800#define UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE__SHIFT 0x1 801#define UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD__SHIFT 0x2 802#define UVD_JPEG_PREEMPT_CMD__PREEMPT_EN_MASK 0x00000001L 803#define UVD_JPEG_PREEMPT_CMD__WAIT_JPEG_JOB_DONE_MASK 0x00000002L 804#define UVD_JPEG_PREEMPT_CMD__PREEMPT_FENCE_CMD_MASK 0x00000004L 805//UVD_JPEG_PREEMPT_FENCE_DATA0 806#define UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0__SHIFT 0x0 807#define UVD_JPEG_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0_MASK 0xFFFFFFFFL 808//UVD_JPEG_PREEMPT_FENCE_DATA1 809#define UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1__SHIFT 0x0 810#define UVD_JPEG_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1_MASK 0xFFFFFFFFL 811//UVD_JRBC_RB_SIZE 812#define UVD_JRBC_RB_SIZE__RB_SIZE__SHIFT 0x4 813#define UVD_JRBC_RB_SIZE__RB_SIZE_MASK 0x00FFFFF0L 814//UVD_JRBC_SCRATCH0 815#define UVD_JRBC_SCRATCH0__SCRATCH0__SHIFT 0x0 816#define UVD_JRBC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL 817 818 819// addressBlock: uvd0_uvd_jrbc_enc_dec 820//UVD_JRBC_ENC_RB_WPTR 821#define UVD_JRBC_ENC_RB_WPTR__RB_WPTR__SHIFT 0x4 822#define UVD_JRBC_ENC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 823//UVD_JRBC_ENC_RB_CNTL 824#define UVD_JRBC_ENC_RB_CNTL__RB_NO_FETCH__SHIFT 0x0 825#define UVD_JRBC_ENC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1 826#define UVD_JRBC_ENC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x4 827#define UVD_JRBC_ENC_RB_CNTL__RB_NO_FETCH_MASK 0x00000001L 828#define UVD_JRBC_ENC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L 829#define UVD_JRBC_ENC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK 0x0007FFF0L 830//UVD_JRBC_ENC_IB_SIZE 831#define UVD_JRBC_ENC_IB_SIZE__IB_SIZE__SHIFT 0x4 832#define UVD_JRBC_ENC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L 833//UVD_JRBC_ENC_URGENT_CNTL 834#define UVD_JRBC_ENC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0 835#define UVD_JRBC_ENC_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L 836//UVD_JRBC_ENC_RB_REF_DATA 837#define UVD_JRBC_ENC_RB_REF_DATA__REF_DATA__SHIFT 0x0 838#define UVD_JRBC_ENC_RB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 839//UVD_JRBC_ENC_RB_COND_RD_TIMER 840#define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 841#define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 842#define UVD_JRBC_ENC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 843#define UVD_JRBC_ENC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 844#define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 845#define UVD_JRBC_ENC_RB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 846#define UVD_JRBC_ENC_RB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 847#define UVD_JRBC_ENC_RB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 848//UVD_JRBC_ENC_SOFT_RESET 849#define UVD_JRBC_ENC_SOFT_RESET__RESET__SHIFT 0x0 850#define UVD_JRBC_ENC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT 0x11 851#define UVD_JRBC_ENC_SOFT_RESET__RESET_MASK 0x00000001L 852#define UVD_JRBC_ENC_SOFT_RESET__SCLK_RESET_STATUS_MASK 0x00020000L 853//UVD_JRBC_ENC_STATUS 854#define UVD_JRBC_ENC_STATUS__RB_JOB_DONE__SHIFT 0x0 855#define UVD_JRBC_ENC_STATUS__IB_JOB_DONE__SHIFT 0x1 856#define UVD_JRBC_ENC_STATUS__RB_ILLEGAL_CMD__SHIFT 0x2 857#define UVD_JRBC_ENC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT 0x3 858#define UVD_JRBC_ENC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT 0x4 859#define UVD_JRBC_ENC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT 0x5 860#define UVD_JRBC_ENC_STATUS__IB_ILLEGAL_CMD__SHIFT 0x6 861#define UVD_JRBC_ENC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT 0x7 862#define UVD_JRBC_ENC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT 0x8 863#define UVD_JRBC_ENC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT 0x9 864#define UVD_JRBC_ENC_STATUS__RB_TRAP_STATUS__SHIFT 0xa 865#define UVD_JRBC_ENC_STATUS__PREEMPT_STATUS__SHIFT 0xb 866#define UVD_JRBC_ENC_STATUS__IB_TRAP_STATUS__SHIFT 0xc 867#define UVD_JRBC_ENC_STATUS__INT_EN__SHIFT 0x10 868#define UVD_JRBC_ENC_STATUS__INT_ACK__SHIFT 0x11 869#define UVD_JRBC_ENC_STATUS__RB_JOB_DONE_MASK 0x00000001L 870#define UVD_JRBC_ENC_STATUS__IB_JOB_DONE_MASK 0x00000002L 871#define UVD_JRBC_ENC_STATUS__RB_ILLEGAL_CMD_MASK 0x00000004L 872#define UVD_JRBC_ENC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK 0x00000008L 873#define UVD_JRBC_ENC_STATUS__RB_MEM_WR_TIMEOUT_MASK 0x00000010L 874#define UVD_JRBC_ENC_STATUS__RB_MEM_RD_TIMEOUT_MASK 0x00000020L 875#define UVD_JRBC_ENC_STATUS__IB_ILLEGAL_CMD_MASK 0x00000040L 876#define UVD_JRBC_ENC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK 0x00000080L 877#define UVD_JRBC_ENC_STATUS__IB_MEM_WR_TIMEOUT_MASK 0x00000100L 878#define UVD_JRBC_ENC_STATUS__IB_MEM_RD_TIMEOUT_MASK 0x00000200L 879#define UVD_JRBC_ENC_STATUS__RB_TRAP_STATUS_MASK 0x00000400L 880#define UVD_JRBC_ENC_STATUS__PREEMPT_STATUS_MASK 0x00000800L 881#define UVD_JRBC_ENC_STATUS__IB_TRAP_STATUS_MASK 0x00001000L 882#define UVD_JRBC_ENC_STATUS__INT_EN_MASK 0x00010000L 883#define UVD_JRBC_ENC_STATUS__INT_ACK_MASK 0x00020000L 884//UVD_JRBC_ENC_RB_RPTR 885#define UVD_JRBC_ENC_RB_RPTR__RB_RPTR__SHIFT 0x4 886#define UVD_JRBC_ENC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 887//UVD_JRBC_ENC_RB_BUF_STATUS 888#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0 889#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10 890#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x18 891#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_VALID_MASK 0x0000FFFFL 892#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x000F0000L 893#define UVD_JRBC_ENC_RB_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x03000000L 894//UVD_JRBC_ENC_IB_BUF_STATUS 895#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_VALID__SHIFT 0x0 896#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x10 897#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x18 898#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FFFFL 899#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x000F0000L 900#define UVD_JRBC_ENC_IB_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x03000000L 901//UVD_JRBC_ENC_IB_SIZE_UPDATE 902#define UVD_JRBC_ENC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4 903#define UVD_JRBC_ENC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L 904//UVD_JRBC_ENC_IB_COND_RD_TIMER 905#define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_TIMER_CNT__SHIFT 0x0 906#define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT__SHIFT 0x10 907#define UVD_JRBC_ENC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN__SHIFT 0x18 908#define UVD_JRBC_ENC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN__SHIFT 0x19 909#define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_TIMER_CNT_MASK 0x0000FFFFL 910#define UVD_JRBC_ENC_IB_COND_RD_TIMER__RETRY_INTERVAL_CNT_MASK 0x00FF0000L 911#define UVD_JRBC_ENC_IB_COND_RD_TIMER__CONTINUOUS_POLL_EN_MASK 0x01000000L 912#define UVD_JRBC_ENC_IB_COND_RD_TIMER__MEM_TIMEOUT_EN_MASK 0x02000000L 913//UVD_JRBC_ENC_IB_REF_DATA 914#define UVD_JRBC_ENC_IB_REF_DATA__REF_DATA__SHIFT 0x0 915#define UVD_JRBC_ENC_IB_REF_DATA__REF_DATA_MASK 0xFFFFFFFFL 916//UVD_JPEG_ENC_PREEMPT_CMD 917#define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_EN__SHIFT 0x0 918#define UVD_JPEG_ENC_PREEMPT_CMD__WAIT_JPEG_JOB_DONE__SHIFT 0x1 919#define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_FENCE_CMD__SHIFT 0x2 920#define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_EN_MASK 0x00000001L 921#define UVD_JPEG_ENC_PREEMPT_CMD__WAIT_JPEG_JOB_DONE_MASK 0x00000002L 922#define UVD_JPEG_ENC_PREEMPT_CMD__PREEMPT_FENCE_CMD_MASK 0x00000004L 923//UVD_JPEG_ENC_PREEMPT_FENCE_DATA0 924#define UVD_JPEG_ENC_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0__SHIFT 0x0 925#define UVD_JPEG_ENC_PREEMPT_FENCE_DATA0__PREEMPT_FENCE_DATA0_MASK 0xFFFFFFFFL 926//UVD_JPEG_ENC_PREEMPT_FENCE_DATA1 927#define UVD_JPEG_ENC_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1__SHIFT 0x0 928#define UVD_JPEG_ENC_PREEMPT_FENCE_DATA1__PREEMPT_FENCE_DATA1_MASK 0xFFFFFFFFL 929//UVD_JRBC_ENC_RB_SIZE 930#define UVD_JRBC_ENC_RB_SIZE__RB_SIZE__SHIFT 0x4 931#define UVD_JRBC_ENC_RB_SIZE__RB_SIZE_MASK 0x00FFFFF0L 932//UVD_JRBC_ENC_SCRATCH0 933#define UVD_JRBC_ENC_SCRATCH0__SCRATCH0__SHIFT 0x0 934#define UVD_JRBC_ENC_SCRATCH0__SCRATCH0_MASK 0xFFFFFFFFL 935 936 937// addressBlock: uvd0_uvd_jmi_dec 938//UVD_JMI_CTRL 939#define UVD_JMI_CTRL__STALL_MC_ARB__SHIFT 0x0 940#define UVD_JMI_CTRL__MASK_MC_URGENT__SHIFT 0x1 941#define UVD_JMI_CTRL__ASSERT_MC_URGENT__SHIFT 0x2 942#define UVD_JMI_CTRL__MC_RD_ARB_WAIT_TIMER__SHIFT 0x8 943#define UVD_JMI_CTRL__MC_WR_ARB_WAIT_TIMER__SHIFT 0x10 944#define UVD_JMI_CTRL__CRC_RESET__SHIFT 0x18 945#define UVD_JMI_CTRL__CRC_SEL__SHIFT 0x19 946#define UVD_JMI_CTRL__STALL_MC_ARB_MASK 0x00000001L 947#define UVD_JMI_CTRL__MASK_MC_URGENT_MASK 0x00000002L 948#define UVD_JMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000004L 949#define UVD_JMI_CTRL__MC_RD_ARB_WAIT_TIMER_MASK 0x0000FF00L 950#define UVD_JMI_CTRL__MC_WR_ARB_WAIT_TIMER_MASK 0x00FF0000L 951#define UVD_JMI_CTRL__CRC_RESET_MASK 0x01000000L 952#define UVD_JMI_CTRL__CRC_SEL_MASK 0x1E000000L 953//UVD_LMI_JRBC_CTRL 954#define UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 955#define UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 956#define UVD_LMI_JRBC_CTRL__RD_MAX_BURST__SHIFT 0x4 957#define UVD_LMI_JRBC_CTRL__WR_MAX_BURST__SHIFT 0x8 958#define UVD_LMI_JRBC_CTRL__RD_SWAP__SHIFT 0x14 959#define UVD_LMI_JRBC_CTRL__WR_SWAP__SHIFT 0x16 960#define UVD_LMI_JRBC_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 961#define UVD_LMI_JRBC_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 962#define UVD_LMI_JRBC_CTRL__RD_MAX_BURST_MASK 0x000000F0L 963#define UVD_LMI_JRBC_CTRL__WR_MAX_BURST_MASK 0x00000F00L 964#define UVD_LMI_JRBC_CTRL__RD_SWAP_MASK 0x00300000L 965#define UVD_LMI_JRBC_CTRL__WR_SWAP_MASK 0x00C00000L 966//UVD_LMI_JPEG_CTRL 967#define UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 968#define UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 969#define UVD_LMI_JPEG_CTRL__RD_MAX_BURST__SHIFT 0x4 970#define UVD_LMI_JPEG_CTRL__WR_MAX_BURST__SHIFT 0x8 971#define UVD_LMI_JPEG_CTRL__RD_SWAP__SHIFT 0x14 972#define UVD_LMI_JPEG_CTRL__WR_SWAP__SHIFT 0x16 973#define UVD_LMI_JPEG_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 974#define UVD_LMI_JPEG_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 975#define UVD_LMI_JPEG_CTRL__RD_MAX_BURST_MASK 0x000000F0L 976#define UVD_LMI_JPEG_CTRL__WR_MAX_BURST_MASK 0x00000F00L 977#define UVD_LMI_JPEG_CTRL__RD_SWAP_MASK 0x00300000L 978#define UVD_LMI_JPEG_CTRL__WR_SWAP_MASK 0x00C00000L 979//UVD_JMI_EJRBC_CTRL 980#define UVD_JMI_EJRBC_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 981#define UVD_JMI_EJRBC_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 982#define UVD_JMI_EJRBC_CTRL__RD_MAX_BURST__SHIFT 0x4 983#define UVD_JMI_EJRBC_CTRL__WR_MAX_BURST__SHIFT 0x8 984#define UVD_JMI_EJRBC_CTRL__RD_SWAP__SHIFT 0x14 985#define UVD_JMI_EJRBC_CTRL__WR_SWAP__SHIFT 0x16 986#define UVD_JMI_EJRBC_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 987#define UVD_JMI_EJRBC_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 988#define UVD_JMI_EJRBC_CTRL__RD_MAX_BURST_MASK 0x000000F0L 989#define UVD_JMI_EJRBC_CTRL__WR_MAX_BURST_MASK 0x00000F00L 990#define UVD_JMI_EJRBC_CTRL__RD_SWAP_MASK 0x00300000L 991#define UVD_JMI_EJRBC_CTRL__WR_SWAP_MASK 0x00C00000L 992//UVD_LMI_EJPEG_CTRL 993#define UVD_LMI_EJPEG_CTRL__ARB_RD_WAIT_EN__SHIFT 0x0 994#define UVD_LMI_EJPEG_CTRL__ARB_WR_WAIT_EN__SHIFT 0x1 995#define UVD_LMI_EJPEG_CTRL__RD_MAX_BURST__SHIFT 0x4 996#define UVD_LMI_EJPEG_CTRL__WR_MAX_BURST__SHIFT 0x8 997#define UVD_LMI_EJPEG_CTRL__RD_SWAP__SHIFT 0x14 998#define UVD_LMI_EJPEG_CTRL__WR_SWAP__SHIFT 0x16 999#define UVD_LMI_EJPEG_CTRL__ARB_RD_WAIT_EN_MASK 0x00000001L 1000#define UVD_LMI_EJPEG_CTRL__ARB_WR_WAIT_EN_MASK 0x00000002L 1001#define UVD_LMI_EJPEG_CTRL__RD_MAX_BURST_MASK 0x000000F0L 1002#define UVD_LMI_EJPEG_CTRL__WR_MAX_BURST_MASK 0x00000F00L 1003#define UVD_LMI_EJPEG_CTRL__RD_SWAP_MASK 0x00300000L 1004#define UVD_LMI_EJPEG_CTRL__WR_SWAP_MASK 0x00C00000L 1005//UVD_LMI_JRBC_IB_VMID 1006#define UVD_LMI_JRBC_IB_VMID__IB_WR_VMID__SHIFT 0x0 1007#define UVD_LMI_JRBC_IB_VMID__IB_RD_VMID__SHIFT 0x4 1008#define UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID__SHIFT 0x8 1009#define UVD_LMI_JRBC_IB_VMID__IB_WR_VMID_MASK 0x0000000FL 1010#define UVD_LMI_JRBC_IB_VMID__IB_RD_VMID_MASK 0x000000F0L 1011#define UVD_LMI_JRBC_IB_VMID__MEM_RD_VMID_MASK 0x00000F00L 1012//UVD_LMI_JRBC_RB_VMID 1013#define UVD_LMI_JRBC_RB_VMID__RB_WR_VMID__SHIFT 0x0 1014#define UVD_LMI_JRBC_RB_VMID__RB_RD_VMID__SHIFT 0x4 1015#define UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID__SHIFT 0x8 1016#define UVD_LMI_JRBC_RB_VMID__RB_WR_VMID_MASK 0x0000000FL 1017#define UVD_LMI_JRBC_RB_VMID__RB_RD_VMID_MASK 0x000000F0L 1018#define UVD_LMI_JRBC_RB_VMID__MEM_RD_VMID_MASK 0x00000F00L 1019//UVD_LMI_JPEG_VMID 1020#define UVD_LMI_JPEG_VMID__JPEG_RD_VMID__SHIFT 0x0 1021#define UVD_LMI_JPEG_VMID__JPEG_WR_VMID__SHIFT 0x4 1022#define UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID__SHIFT 0x8 1023#define UVD_LMI_JPEG_VMID__JPEG_RD_VMID_MASK 0x0000000FL 1024#define UVD_LMI_JPEG_VMID__JPEG_WR_VMID_MASK 0x000000F0L 1025#define UVD_LMI_JPEG_VMID__ATOMIC_USER0_WR_VMID_MASK 0x00000F00L 1026//UVD_JMI_ENC_JRBC_IB_VMID 1027#define UVD_JMI_ENC_JRBC_IB_VMID__IB_WR_VMID__SHIFT 0x0 1028#define UVD_JMI_ENC_JRBC_IB_VMID__IB_RD_VMID__SHIFT 0x4 1029#define UVD_JMI_ENC_JRBC_IB_VMID__MEM_RD_VMID__SHIFT 0x8 1030#define UVD_JMI_ENC_JRBC_IB_VMID__IB_WR_VMID_MASK 0x0000000FL 1031#define UVD_JMI_ENC_JRBC_IB_VMID__IB_RD_VMID_MASK 0x000000F0L 1032#define UVD_JMI_ENC_JRBC_IB_VMID__MEM_RD_VMID_MASK 0x00000F00L 1033//UVD_JMI_ENC_JRBC_RB_VMID 1034#define UVD_JMI_ENC_JRBC_RB_VMID__RB_WR_VMID__SHIFT 0x0 1035#define UVD_JMI_ENC_JRBC_RB_VMID__RB_RD_VMID__SHIFT 0x4 1036#define UVD_JMI_ENC_JRBC_RB_VMID__MEM_RD_VMID__SHIFT 0x8 1037#define UVD_JMI_ENC_JRBC_RB_VMID__RB_WR_VMID_MASK 0x0000000FL 1038#define UVD_JMI_ENC_JRBC_RB_VMID__RB_RD_VMID_MASK 0x000000F0L 1039#define UVD_JMI_ENC_JRBC_RB_VMID__MEM_RD_VMID_MASK 0x00000F00L 1040//UVD_JMI_ENC_JPEG_VMID 1041#define UVD_JMI_ENC_JPEG_VMID__PEL_RD_VMID__SHIFT 0x0 1042#define UVD_JMI_ENC_JPEG_VMID__BS_WR_VMID__SHIFT 0x5 1043#define UVD_JMI_ENC_JPEG_VMID__SCALAR_RD_VMID__SHIFT 0xa 1044#define UVD_JMI_ENC_JPEG_VMID__SCALAR_WR_VMID__SHIFT 0xf 1045#define UVD_JMI_ENC_JPEG_VMID__HUFF_FENCE_VMID__SHIFT 0x13 1046#define UVD_JMI_ENC_JPEG_VMID__ATOMIC_USER1_WR_VMID__SHIFT 0x17 1047#define UVD_JMI_ENC_JPEG_VMID__PEL_RD_VMID_MASK 0x0000000FL 1048#define UVD_JMI_ENC_JPEG_VMID__BS_WR_VMID_MASK 0x000001E0L 1049#define UVD_JMI_ENC_JPEG_VMID__SCALAR_RD_VMID_MASK 0x00003C00L 1050#define UVD_JMI_ENC_JPEG_VMID__SCALAR_WR_VMID_MASK 0x00078000L 1051#define UVD_JMI_ENC_JPEG_VMID__HUFF_FENCE_VMID_MASK 0x00780000L 1052#define UVD_JMI_ENC_JPEG_VMID__ATOMIC_USER1_WR_VMID_MASK 0x07800000L 1053//UVD_JMI_PERFMON_CTRL 1054#define UVD_JMI_PERFMON_CTRL__PERFMON_STATE__SHIFT 0x0 1055#define UVD_JMI_PERFMON_CTRL__PERFMON_SEL__SHIFT 0x8 1056#define UVD_JMI_PERFMON_CTRL__PERFMON_STATE_MASK 0x00000003L 1057#define UVD_JMI_PERFMON_CTRL__PERFMON_SEL_MASK 0x00000F00L 1058//UVD_JMI_PERFMON_COUNT_LO 1059#define UVD_JMI_PERFMON_COUNT_LO__PERFMON_COUNT__SHIFT 0x0 1060#define UVD_JMI_PERFMON_COUNT_LO__PERFMON_COUNT_MASK 0xFFFFFFFFL 1061//UVD_JMI_PERFMON_COUNT_HI 1062#define UVD_JMI_PERFMON_COUNT_HI__PERFMON_COUNT__SHIFT 0x0 1063#define UVD_JMI_PERFMON_COUNT_HI__PERFMON_COUNT_MASK 0x0000FFFFL 1064//UVD_LMI_JPEG_READ_64BIT_BAR_LOW 1065#define UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1066#define UVD_LMI_JPEG_READ_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1067//UVD_LMI_JPEG_READ_64BIT_BAR_HIGH 1068#define UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1069#define UVD_LMI_JPEG_READ_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1070//UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 1071#define UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1072#define UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1073//UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 1074#define UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1075#define UVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1076//UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW 1077#define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1078#define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1079//UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 1080#define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1081#define UVD_LMI_JPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1082//UVD_LMI_JRBC_RB_64BIT_BAR_LOW 1083#define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1084#define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1085//UVD_LMI_JRBC_RB_64BIT_BAR_HIGH 1086#define UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1087#define UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1088//UVD_LMI_JRBC_IB_64BIT_BAR_LOW 1089#define UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1090#define UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1091//UVD_LMI_JRBC_IB_64BIT_BAR_HIGH 1092#define UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1093#define UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1094//UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW 1095#define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1096#define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1097//UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH 1098#define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1099#define UVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1100//UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW 1101#define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1102#define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1103//UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH 1104#define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1105#define UVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1106//UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW 1107#define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1108#define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1109//UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH 1110#define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1111#define UVD_LMI_JRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1112//UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW 1113#define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1114#define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1115//UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH 1116#define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1117#define UVD_LMI_JRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1118//UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW 1119#define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1120#define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1121//UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH 1122#define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1123#define UVD_LMI_EJPEG_PREEMPT_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1124//UVD_LMI_EJRBC_RB_64BIT_BAR_LOW 1125#define UVD_LMI_EJRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1126#define UVD_LMI_EJRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1127//UVD_LMI_EJRBC_RB_64BIT_BAR_HIGH 1128#define UVD_LMI_EJRBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1129#define UVD_LMI_EJRBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1130//UVD_LMI_EJRBC_IB_64BIT_BAR_LOW 1131#define UVD_LMI_EJRBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1132#define UVD_LMI_EJRBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1133//UVD_LMI_EJRBC_IB_64BIT_BAR_HIGH 1134#define UVD_LMI_EJRBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1135#define UVD_LMI_EJRBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1136//UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW 1137#define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1138#define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1139//UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH 1140#define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1141#define UVD_LMI_EJRBC_RB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1142//UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW 1143#define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1144#define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1145//UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH 1146#define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1147#define UVD_LMI_EJRBC_RB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1148//UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW 1149#define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1150#define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1151//UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH 1152#define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1153#define UVD_LMI_EJRBC_IB_MEM_WR_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1154//UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW 1155#define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1156#define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1157//UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH 1158#define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1159#define UVD_LMI_EJRBC_IB_MEM_RD_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1160//UVD_LMI_JPEG_PREEMPT_VMID 1161#define UVD_LMI_JPEG_PREEMPT_VMID__VMID__SHIFT 0x0 1162#define UVD_LMI_JPEG_PREEMPT_VMID__VMID_MASK 0x0000000FL 1163//UVD_LMI_ENC_JPEG_PREEMPT_VMID 1164#define UVD_LMI_ENC_JPEG_PREEMPT_VMID__VMID__SHIFT 0x0 1165#define UVD_LMI_ENC_JPEG_PREEMPT_VMID__VMID_MASK 0x0000000FL 1166//UVD_LMI_JPEG2_VMID 1167#define UVD_LMI_JPEG2_VMID__JPEG2_RD_VMID__SHIFT 0x0 1168#define UVD_LMI_JPEG2_VMID__JPEG2_WR_VMID__SHIFT 0x4 1169#define UVD_LMI_JPEG2_VMID__JPEG2_RD_VMID_MASK 0x0000000FL 1170#define UVD_LMI_JPEG2_VMID__JPEG2_WR_VMID_MASK 0x000000F0L 1171//UVD_LMI_JPEG2_READ_64BIT_BAR_LOW 1172#define UVD_LMI_JPEG2_READ_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1173#define UVD_LMI_JPEG2_READ_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1174//UVD_LMI_JPEG2_READ_64BIT_BAR_HIGH 1175#define UVD_LMI_JPEG2_READ_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1176#define UVD_LMI_JPEG2_READ_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1177//UVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW 1178#define UVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1179#define UVD_LMI_JPEG2_WRITE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1180//UVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH 1181#define UVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1182#define UVD_LMI_JPEG2_WRITE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1183//UVD_LMI_JPEG_CTRL2 1184#define UVD_LMI_JPEG_CTRL2__ARB_RD_WAIT_EN__SHIFT 0x0 1185#define UVD_LMI_JPEG_CTRL2__ARB_WR_WAIT_EN__SHIFT 0x1 1186#define UVD_LMI_JPEG_CTRL2__RD_MAX_BURST__SHIFT 0x4 1187#define UVD_LMI_JPEG_CTRL2__WR_MAX_BURST__SHIFT 0x8 1188#define UVD_LMI_JPEG_CTRL2__RD_SWAP__SHIFT 0x14 1189#define UVD_LMI_JPEG_CTRL2__WR_SWAP__SHIFT 0x16 1190#define UVD_LMI_JPEG_CTRL2__ARB_RD_WAIT_EN_MASK 0x00000001L 1191#define UVD_LMI_JPEG_CTRL2__ARB_WR_WAIT_EN_MASK 0x00000002L 1192#define UVD_LMI_JPEG_CTRL2__RD_MAX_BURST_MASK 0x000000F0L 1193#define UVD_LMI_JPEG_CTRL2__WR_MAX_BURST_MASK 0x00000F00L 1194#define UVD_LMI_JPEG_CTRL2__RD_SWAP_MASK 0x00300000L 1195#define UVD_LMI_JPEG_CTRL2__WR_SWAP_MASK 0x00C00000L 1196//UVD_JMI_DEC_SWAP_CNTL 1197#define UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 1198#define UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 1199#define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP__SHIFT 0x4 1200#define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP__SHIFT 0x6 1201#define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP__SHIFT 0x8 1202#define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT 0xa 1203#define UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP__SHIFT 0xc 1204#define UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP__SHIFT 0xe 1205#define UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP__SHIFT 0x10 1206#define UVD_JMI_DEC_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L 1207#define UVD_JMI_DEC_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL 1208#define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_WR_MC_SWAP_MASK 0x00000030L 1209#define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_WR_MC_SWAP_MASK 0x000000C0L 1210#define UVD_JMI_DEC_SWAP_CNTL__RB_MEM_RD_MC_SWAP_MASK 0x00000300L 1211#define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP_MASK 0x00000C00L 1212#define UVD_JMI_DEC_SWAP_CNTL__PREEMPT_WR_MC_SWAP_MASK 0x00003000L 1213#define UVD_JMI_DEC_SWAP_CNTL__JPEG_RD_MC_SWAP_MASK 0x0000C000L 1214#define UVD_JMI_DEC_SWAP_CNTL__JPEG_WR_MC_SWAP_MASK 0x00030000L 1215//UVD_JMI_ENC_SWAP_CNTL 1216#define UVD_JMI_ENC_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 1217#define UVD_JMI_ENC_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 1218#define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_WR_MC_SWAP__SHIFT 0x4 1219#define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_WR_MC_SWAP__SHIFT 0x6 1220#define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_RD_MC_SWAP__SHIFT 0x8 1221#define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT 0xa 1222#define UVD_JMI_ENC_SWAP_CNTL__PREEMPT_WR_MC_SWAP__SHIFT 0xc 1223#define UVD_JMI_ENC_SWAP_CNTL__PEL_RD_MC_SWAP__SHIFT 0xe 1224#define UVD_JMI_ENC_SWAP_CNTL__BS_WR_MC_SWAP__SHIFT 0x10 1225#define UVD_JMI_ENC_SWAP_CNTL__SCALAR_RD_MC_SWAP__SHIFT 0x12 1226#define UVD_JMI_ENC_SWAP_CNTL__SCALAR_WR_MC_SWAP__SHIFT 0x14 1227#define UVD_JMI_ENC_SWAP_CNTL__HUFF_FENCE_MC_SWAP__SHIFT 0x16 1228#define UVD_JMI_ENC_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L 1229#define UVD_JMI_ENC_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL 1230#define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_WR_MC_SWAP_MASK 0x00000030L 1231#define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_WR_MC_SWAP_MASK 0x000000C0L 1232#define UVD_JMI_ENC_SWAP_CNTL__RB_MEM_RD_MC_SWAP_MASK 0x00000300L 1233#define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_RD_MC_SWAP_MASK 0x00000C00L 1234#define UVD_JMI_ENC_SWAP_CNTL__PREEMPT_WR_MC_SWAP_MASK 0x00003000L 1235#define UVD_JMI_ENC_SWAP_CNTL__PEL_RD_MC_SWAP_MASK 0x0000C000L 1236#define UVD_JMI_ENC_SWAP_CNTL__BS_WR_MC_SWAP_MASK 0x00030000L 1237#define UVD_JMI_ENC_SWAP_CNTL__SCALAR_RD_MC_SWAP_MASK 0x000C0000L 1238#define UVD_JMI_ENC_SWAP_CNTL__SCALAR_WR_MC_SWAP_MASK 0x00300000L 1239#define UVD_JMI_ENC_SWAP_CNTL__HUFF_FENCE_MC_SWAP_MASK 0x00C00000L 1240//UVD_JMI_CNTL 1241#define UVD_JMI_CNTL__SOFT_RESET__SHIFT 0x0 1242#define UVD_JMI_CNTL__MC_RD_REQ_RET_MAX__SHIFT 0x8 1243#define UVD_JMI_CNTL__SOFT_RESET_MASK 0x00000001L 1244#define UVD_JMI_CNTL__MC_RD_REQ_RET_MAX_MASK 0x0003FF00L 1245//UVD_JMI_HUFF_FENCE_64BIT_BAR_LOW 1246#define UVD_JMI_HUFF_FENCE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1247#define UVD_JMI_HUFF_FENCE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1248//UVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH 1249#define UVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1250#define UVD_JMI_HUFF_FENCE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1251//UVD_JMI_DEC_SWAP_CNTL2 1252#define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_RD_MC_SWAP__SHIFT 0x0 1253#define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_WR_MC_SWAP__SHIFT 0x2 1254#define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_RD_MC_SWAP_MASK 0x00000003L 1255#define UVD_JMI_DEC_SWAP_CNTL2__JPEG2_WR_MC_SWAP_MASK 0x0000000CL 1256 1257 1258// addressBlock: uvd0_uvd_jpeg_common_dec 1259//JPEG_SOFT_RESET_STATUS 1260#define JPEG_SOFT_RESET_STATUS__JPEG_DEC_RESET_STATUS__SHIFT 0x0 1261#define JPEG_SOFT_RESET_STATUS__JPEG2_DEC_RESET_STATUS__SHIFT 0x1 1262#define JPEG_SOFT_RESET_STATUS__DJRBC_RESET_STATUS__SHIFT 0x2 1263#define JPEG_SOFT_RESET_STATUS__JPEG_ENC_RESET_STATUS__SHIFT 0x3 1264#define JPEG_SOFT_RESET_STATUS__EJRBC_RESET_STATUS__SHIFT 0x4 1265#define JPEG_SOFT_RESET_STATUS__JMCIF_RESET_STATUS__SHIFT 0x5 1266#define JPEG_SOFT_RESET_STATUS__JPEG_DEC_RESET_STATUS_MASK 0x00000001L 1267#define JPEG_SOFT_RESET_STATUS__JPEG2_DEC_RESET_STATUS_MASK 0x00000002L 1268#define JPEG_SOFT_RESET_STATUS__DJRBC_RESET_STATUS_MASK 0x00000004L 1269#define JPEG_SOFT_RESET_STATUS__JPEG_ENC_RESET_STATUS_MASK 0x00000008L 1270#define JPEG_SOFT_RESET_STATUS__EJRBC_RESET_STATUS_MASK 0x00000010L 1271#define JPEG_SOFT_RESET_STATUS__JMCIF_RESET_STATUS_MASK 0x00000020L 1272//JPEG_SYS_INT_EN 1273#define JPEG_SYS_INT_EN__DJPEG_CORE__SHIFT 0x0 1274#define JPEG_SYS_INT_EN__DJRBC__SHIFT 0x1 1275#define JPEG_SYS_INT_EN__DJPEG_PF_RPT__SHIFT 0x2 1276#define JPEG_SYS_INT_EN__EJPEG_PF_RPT__SHIFT 0x3 1277#define JPEG_SYS_INT_EN__EJPEG_CORE__SHIFT 0x4 1278#define JPEG_SYS_INT_EN__EJRBC__SHIFT 0x5 1279#define JPEG_SYS_INT_EN__DJPEG_CORE2__SHIFT 0x6 1280#define JPEG_SYS_INT_EN__DJPEG_CORE_MASK 0x00000001L 1281#define JPEG_SYS_INT_EN__DJRBC_MASK 0x00000002L 1282#define JPEG_SYS_INT_EN__DJPEG_PF_RPT_MASK 0x00000004L 1283#define JPEG_SYS_INT_EN__EJPEG_PF_RPT_MASK 0x00000008L 1284#define JPEG_SYS_INT_EN__EJPEG_CORE_MASK 0x00000010L 1285#define JPEG_SYS_INT_EN__EJRBC_MASK 0x00000020L 1286#define JPEG_SYS_INT_EN__DJPEG_CORE2_MASK 0x00000040L 1287//JPEG_SYS_INT_STATUS 1288#define JPEG_SYS_INT_STATUS__DJPEG_CORE__SHIFT 0x0 1289#define JPEG_SYS_INT_STATUS__DJRBC__SHIFT 0x1 1290#define JPEG_SYS_INT_STATUS__DJPEG_PF_RPT__SHIFT 0x2 1291#define JPEG_SYS_INT_STATUS__EJPEG_PF_RPT__SHIFT 0x3 1292#define JPEG_SYS_INT_STATUS__EJPEG_CORE__SHIFT 0x4 1293#define JPEG_SYS_INT_STATUS__EJRBC__SHIFT 0x5 1294#define JPEG_SYS_INT_STATUS__DJPEG_CORE2__SHIFT 0x6 1295#define JPEG_SYS_INT_STATUS__DJPEG_CORE_MASK 0x00000001L 1296#define JPEG_SYS_INT_STATUS__DJRBC_MASK 0x00000002L 1297#define JPEG_SYS_INT_STATUS__DJPEG_PF_RPT_MASK 0x00000004L 1298#define JPEG_SYS_INT_STATUS__EJPEG_PF_RPT_MASK 0x00000008L 1299#define JPEG_SYS_INT_STATUS__EJPEG_CORE_MASK 0x00000010L 1300#define JPEG_SYS_INT_STATUS__EJRBC_MASK 0x00000020L 1301#define JPEG_SYS_INT_STATUS__DJPEG_CORE2_MASK 0x00000040L 1302//JPEG_SYS_INT_ACK 1303#define JPEG_SYS_INT_ACK__DJPEG_CORE__SHIFT 0x0 1304#define JPEG_SYS_INT_ACK__DJRBC__SHIFT 0x1 1305#define JPEG_SYS_INT_ACK__DJPEG_PF_RPT__SHIFT 0x2 1306#define JPEG_SYS_INT_ACK__EJPEG_PF_RPT__SHIFT 0x3 1307#define JPEG_SYS_INT_ACK__EJPEG_CORE__SHIFT 0x4 1308#define JPEG_SYS_INT_ACK__EJRBC__SHIFT 0x5 1309#define JPEG_SYS_INT_ACK__DJPEG_CORE2__SHIFT 0x6 1310#define JPEG_SYS_INT_ACK__DJPEG_CORE_MASK 0x00000001L 1311#define JPEG_SYS_INT_ACK__DJRBC_MASK 0x00000002L 1312#define JPEG_SYS_INT_ACK__DJPEG_PF_RPT_MASK 0x00000004L 1313#define JPEG_SYS_INT_ACK__EJPEG_PF_RPT_MASK 0x00000008L 1314#define JPEG_SYS_INT_ACK__EJPEG_CORE_MASK 0x00000010L 1315#define JPEG_SYS_INT_ACK__EJRBC_MASK 0x00000020L 1316#define JPEG_SYS_INT_ACK__DJPEG_CORE2_MASK 0x00000040L 1317//JPEG_MASTINT_EN 1318#define JPEG_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 1319#define JPEG_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 1320#define JPEG_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L 1321#define JPEG_MASTINT_EN__INT_OVERRUN_MASK 0x007FFFF0L 1322//JPEG_IH_CTRL 1323#define JPEG_IH_CTRL__IH_SOFT_RESET__SHIFT 0x0 1324#define JPEG_IH_CTRL__IH_STALL_EN__SHIFT 0x1 1325#define JPEG_IH_CTRL__IH_STATUS_CLEAN__SHIFT 0x2 1326#define JPEG_IH_CTRL__IH_VMID__SHIFT 0x3 1327#define JPEG_IH_CTRL__IH_USER_DATA__SHIFT 0x7 1328#define JPEG_IH_CTRL__IH_RINGID__SHIFT 0x13 1329#define JPEG_IH_CTRL__IH_SOFT_RESET_MASK 0x00000001L 1330#define JPEG_IH_CTRL__IH_STALL_EN_MASK 0x00000002L 1331#define JPEG_IH_CTRL__IH_STATUS_CLEAN_MASK 0x00000004L 1332#define JPEG_IH_CTRL__IH_VMID_MASK 0x00000078L 1333#define JPEG_IH_CTRL__IH_USER_DATA_MASK 0x0007FF80L 1334#define JPEG_IH_CTRL__IH_RINGID_MASK 0x07F80000L 1335//JRBBM_ARB_CTRL 1336#define JRBBM_ARB_CTRL__DJRBC_DROP__SHIFT 0x0 1337#define JRBBM_ARB_CTRL__EJRBC_DROP__SHIFT 0x1 1338#define JRBBM_ARB_CTRL__SRBM_DROP__SHIFT 0x2 1339#define JRBBM_ARB_CTRL__DJRBC_DROP_MASK 0x00000001L 1340#define JRBBM_ARB_CTRL__EJRBC_DROP_MASK 0x00000002L 1341#define JRBBM_ARB_CTRL__SRBM_DROP_MASK 0x00000004L 1342 1343 1344// addressBlock: uvd0_uvd_jpeg_common_sclk_dec 1345//JPEG_CGC_GATE 1346#define JPEG_CGC_GATE__JPEG_DEC__SHIFT 0x0 1347#define JPEG_CGC_GATE__JPEG2_DEC__SHIFT 0x1 1348#define JPEG_CGC_GATE__JPEG_ENC__SHIFT 0x2 1349#define JPEG_CGC_GATE__JMCIF__SHIFT 0x3 1350#define JPEG_CGC_GATE__JRBBM__SHIFT 0x4 1351#define JPEG_CGC_GATE__JPEG_DEC_MASK 0x00000001L 1352#define JPEG_CGC_GATE__JPEG2_DEC_MASK 0x00000002L 1353#define JPEG_CGC_GATE__JPEG_ENC_MASK 0x00000004L 1354#define JPEG_CGC_GATE__JMCIF_MASK 0x00000008L 1355#define JPEG_CGC_GATE__JRBBM_MASK 0x00000010L 1356//JPEG_CGC_CTRL 1357#define JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 1358#define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x1 1359#define JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x5 1360#define JPEG_CGC_CTRL__DYN_OCLK_RAMP_EN__SHIFT 0xa 1361#define JPEG_CGC_CTRL__DYN_RCLK_RAMP_EN__SHIFT 0xb 1362#define JPEG_CGC_CTRL__GATER_DIV_ID__SHIFT 0xc 1363#define JPEG_CGC_CTRL__JPEG_DEC_MODE__SHIFT 0x10 1364#define JPEG_CGC_CTRL__JPEG2_DEC_MODE__SHIFT 0x11 1365#define JPEG_CGC_CTRL__JPEG_ENC_MODE__SHIFT 0x12 1366#define JPEG_CGC_CTRL__JMCIF_MODE__SHIFT 0x13 1367#define JPEG_CGC_CTRL__JRBBM_MODE__SHIFT 0x14 1368#define JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L 1369#define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000001EL 1370#define JPEG_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000003E0L 1371#define JPEG_CGC_CTRL__DYN_OCLK_RAMP_EN_MASK 0x00000400L 1372#define JPEG_CGC_CTRL__DYN_RCLK_RAMP_EN_MASK 0x00000800L 1373#define JPEG_CGC_CTRL__GATER_DIV_ID_MASK 0x00007000L 1374#define JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK 0x00010000L 1375#define JPEG_CGC_CTRL__JPEG2_DEC_MODE_MASK 0x00020000L 1376#define JPEG_CGC_CTRL__JPEG_ENC_MODE_MASK 0x00040000L 1377#define JPEG_CGC_CTRL__JMCIF_MODE_MASK 0x00080000L 1378#define JPEG_CGC_CTRL__JRBBM_MODE_MASK 0x00100000L 1379//JPEG_CGC_STATUS 1380#define JPEG_CGC_STATUS__JPEG_DEC_VCLK_ACTIVE__SHIFT 0x0 1381#define JPEG_CGC_STATUS__JPEG_DEC_SCLK_ACTIVE__SHIFT 0x1 1382#define JPEG_CGC_STATUS__JPEG2_DEC_VCLK_ACTIVE__SHIFT 0x2 1383#define JPEG_CGC_STATUS__JPEG2_DEC_SCLK_ACTIVE__SHIFT 0x3 1384#define JPEG_CGC_STATUS__JPEG_ENC_VCLK_ACTIVE__SHIFT 0x4 1385#define JPEG_CGC_STATUS__JPEG_ENC_SCLK_ACTIVE__SHIFT 0x5 1386#define JPEG_CGC_STATUS__JMCIF_SCLK_ACTIVE__SHIFT 0x6 1387#define JPEG_CGC_STATUS__JRBBM_VCLK_ACTIVE__SHIFT 0x7 1388#define JPEG_CGC_STATUS__JRBBM_SCLK_ACTIVE__SHIFT 0x8 1389#define JPEG_CGC_STATUS__JPEG_DEC_VCLK_ACTIVE_MASK 0x00000001L 1390#define JPEG_CGC_STATUS__JPEG_DEC_SCLK_ACTIVE_MASK 0x00000002L 1391#define JPEG_CGC_STATUS__JPEG2_DEC_VCLK_ACTIVE_MASK 0x00000004L 1392#define JPEG_CGC_STATUS__JPEG2_DEC_SCLK_ACTIVE_MASK 0x00000008L 1393#define JPEG_CGC_STATUS__JPEG_ENC_VCLK_ACTIVE_MASK 0x00000010L 1394#define JPEG_CGC_STATUS__JPEG_ENC_SCLK_ACTIVE_MASK 0x00000020L 1395#define JPEG_CGC_STATUS__JMCIF_SCLK_ACTIVE_MASK 0x00000040L 1396#define JPEG_CGC_STATUS__JRBBM_VCLK_ACTIVE_MASK 0x00000080L 1397#define JPEG_CGC_STATUS__JRBBM_SCLK_ACTIVE_MASK 0x00000100L 1398//JPEG_COMN_CGC_MEM_CTRL 1399#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_LS_EN__SHIFT 0x0 1400#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_DS_EN__SHIFT 0x1 1401#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_SD_EN__SHIFT 0x2 1402#define JPEG_COMN_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT 0x10 1403#define JPEG_COMN_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT 0x14 1404#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_LS_EN_MASK 0x00000001L 1405#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_DS_EN_MASK 0x00000002L 1406#define JPEG_COMN_CGC_MEM_CTRL__JMCIF_SD_EN_MASK 0x00000004L 1407#define JPEG_COMN_CGC_MEM_CTRL__LS_SET_DELAY_MASK 0x000F0000L 1408#define JPEG_COMN_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK 0x00F00000L 1409//JPEG_DEC_CGC_MEM_CTRL 1410#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_LS_EN__SHIFT 0x0 1411#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_DS_EN__SHIFT 0x1 1412#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_SD_EN__SHIFT 0x2 1413#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_LS_EN_MASK 0x00000001L 1414#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_DS_EN_MASK 0x00000002L 1415#define JPEG_DEC_CGC_MEM_CTRL__JPEG_DEC_SD_EN_MASK 0x00000004L 1416//JPEG2_DEC_CGC_MEM_CTRL 1417#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_LS_EN__SHIFT 0x0 1418#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_DS_EN__SHIFT 0x1 1419#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_SD_EN__SHIFT 0x2 1420#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_LS_EN_MASK 0x00000001L 1421#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_DS_EN_MASK 0x00000002L 1422#define JPEG2_DEC_CGC_MEM_CTRL__JPEG2_DEC_SD_EN_MASK 0x00000004L 1423//JPEG_ENC_CGC_MEM_CTRL 1424#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_LS_EN__SHIFT 0x0 1425#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_DS_EN__SHIFT 0x1 1426#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_SD_EN__SHIFT 0x2 1427#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_LS_EN_MASK 0x00000001L 1428#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_DS_EN_MASK 0x00000002L 1429#define JPEG_ENC_CGC_MEM_CTRL__JPEG_ENC_SD_EN_MASK 0x00000004L 1430//JPEG_SOFT_RESET2 1431#define JPEG_SOFT_RESET2__ATOMIC_SOFT_RESET__SHIFT 0x0 1432#define JPEG_SOFT_RESET2__ATOMIC_SOFT_RESET_MASK 0x00000001L 1433//JPEG_PERF_BANK_CONF 1434#define JPEG_PERF_BANK_CONF__RESET__SHIFT 0x0 1435#define JPEG_PERF_BANK_CONF__PEEK__SHIFT 0x8 1436#define JPEG_PERF_BANK_CONF__CONCATENATE__SHIFT 0x10 1437#define JPEG_PERF_BANK_CONF__RESET_MASK 0x0000000FL 1438#define JPEG_PERF_BANK_CONF__PEEK_MASK 0x00000F00L 1439#define JPEG_PERF_BANK_CONF__CONCATENATE_MASK 0x00030000L 1440//JPEG_PERF_BANK_EVENT_SEL 1441#define JPEG_PERF_BANK_EVENT_SEL__SEL0__SHIFT 0x0 1442#define JPEG_PERF_BANK_EVENT_SEL__SEL1__SHIFT 0x8 1443#define JPEG_PERF_BANK_EVENT_SEL__SEL2__SHIFT 0x10 1444#define JPEG_PERF_BANK_EVENT_SEL__SEL3__SHIFT 0x18 1445#define JPEG_PERF_BANK_EVENT_SEL__SEL0_MASK 0x000000FFL 1446#define JPEG_PERF_BANK_EVENT_SEL__SEL1_MASK 0x0000FF00L 1447#define JPEG_PERF_BANK_EVENT_SEL__SEL2_MASK 0x00FF0000L 1448#define JPEG_PERF_BANK_EVENT_SEL__SEL3_MASK 0xFF000000L 1449//JPEG_PERF_BANK_COUNT0 1450#define JPEG_PERF_BANK_COUNT0__COUNT__SHIFT 0x0 1451#define JPEG_PERF_BANK_COUNT0__COUNT_MASK 0xFFFFFFFFL 1452//JPEG_PERF_BANK_COUNT1 1453#define JPEG_PERF_BANK_COUNT1__COUNT__SHIFT 0x0 1454#define JPEG_PERF_BANK_COUNT1__COUNT_MASK 0xFFFFFFFFL 1455//JPEG_PERF_BANK_COUNT2 1456#define JPEG_PERF_BANK_COUNT2__COUNT__SHIFT 0x0 1457#define JPEG_PERF_BANK_COUNT2__COUNT_MASK 0xFFFFFFFFL 1458//JPEG_PERF_BANK_COUNT3 1459#define JPEG_PERF_BANK_COUNT3__COUNT__SHIFT 0x0 1460#define JPEG_PERF_BANK_COUNT3__COUNT_MASK 0xFFFFFFFFL 1461 1462 1463// addressBlock: uvd0_uvd_pg_dec 1464//UVD_PGFSM_CONFIG 1465#define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 0x0 1466#define UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 0x2 1467#define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 0x4 1468#define UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 0x6 1469#define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 0x8 1470#define UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 0xa 1471#define UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 0xc 1472#define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 0xe 1473#define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 0x10 1474#define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 0x12 1475#define UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT 0x14 1476#define UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG__SHIFT 0x16 1477#define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG_MASK 0x00000003L 1478#define UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG_MASK 0x0000000CL 1479#define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG_MASK 0x00000030L 1480#define UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG_MASK 0x000000C0L 1481#define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG_MASK 0x00000300L 1482#define UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG_MASK 0x00000C00L 1483#define UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG_MASK 0x00003000L 1484#define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG_MASK 0x0000C000L 1485#define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG_MASK 0x00030000L 1486#define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG_MASK 0x000C0000L 1487#define UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG_MASK 0x00300000L 1488#define UVD_PGFSM_CONFIG__UVDJ_PWR_CONFIG_MASK 0x00C00000L 1489//UVD_PGFSM_STATUS 1490#define UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 0x0 1491#define UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 0x2 1492#define UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 0x4 1493#define UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 0x6 1494#define UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 0x8 1495#define UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT 0xa 1496#define UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT 0xc 1497#define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 0xe 1498#define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 0x10 1499#define UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 0x12 1500#define UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT 0x14 1501#define UVD_PGFSM_STATUS__UVDJ_PWR_STATUS__SHIFT 0x16 1502#define UVD_PGFSM_STATUS__UVDM_PWR_STATUS_MASK 0x00000003L 1503#define UVD_PGFSM_STATUS__UVDU_PWR_STATUS_MASK 0x0000000CL 1504#define UVD_PGFSM_STATUS__UVDF_PWR_STATUS_MASK 0x00000030L 1505#define UVD_PGFSM_STATUS__UVDC_PWR_STATUS_MASK 0x000000C0L 1506#define UVD_PGFSM_STATUS__UVDB_PWR_STATUS_MASK 0x00000300L 1507#define UVD_PGFSM_STATUS__UVDIL_PWR_STATUS_MASK 0x00000C00L 1508#define UVD_PGFSM_STATUS__UVDIR_PWR_STATUS_MASK 0x00003000L 1509#define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS_MASK 0x0000C000L 1510#define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS_MASK 0x00030000L 1511#define UVD_PGFSM_STATUS__UVDE_PWR_STATUS_MASK 0x000C0000L 1512#define UVD_PGFSM_STATUS__UVDW_PWR_STATUS_MASK 0x00300000L 1513#define UVD_PGFSM_STATUS__UVDJ_PWR_STATUS_MASK 0x00C00000L 1514//UVD_POWER_STATUS 1515#define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x0 1516#define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2 1517#define UVD_POWER_STATUS__UVD_CG_MODE__SHIFT 0x4 1518#define UVD_POWER_STATUS__UVD_PG_EN__SHIFT 0x8 1519#define UVD_POWER_STATUS__RBC_SNOOP_DIS__SHIFT 0x9 1520#define UVD_POWER_STATUS__SW_RB_SNOOP_DIS__SHIFT 0xb 1521#define UVD_POWER_STATUS__STALL_DPG_POWER_UP__SHIFT 0x1f 1522#define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x00000003L 1523#define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x00000004L 1524#define UVD_POWER_STATUS__UVD_CG_MODE_MASK 0x00000030L 1525#define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x00000100L 1526#define UVD_POWER_STATUS__RBC_SNOOP_DIS_MASK 0x00000200L 1527#define UVD_POWER_STATUS__SW_RB_SNOOP_DIS_MASK 0x00000800L 1528#define UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK 0x80000000L 1529//UVD_PG_IND_INDEX 1530#define UVD_PG_IND_INDEX__INDEX__SHIFT 0x0 1531#define UVD_PG_IND_INDEX__INDEX_MASK 0x0000003FL 1532//UVD_PG_IND_DATA 1533#define UVD_PG_IND_DATA__DATA__SHIFT 0x0 1534#define UVD_PG_IND_DATA__DATA_MASK 0xFFFFFFFFL 1535//CC_UVD_HARVESTING 1536#define CC_UVD_HARVESTING__MMSCH_DISABLE__SHIFT 0x0 1537#define CC_UVD_HARVESTING__UVD_DISABLE__SHIFT 0x1 1538#define CC_UVD_HARVESTING__MMSCH_DISABLE_MASK 0x00000001L 1539#define CC_UVD_HARVESTING__UVD_DISABLE_MASK 0x00000002L 1540//UVD_JPEG_POWER_STATUS 1541#define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS__SHIFT 0x0 1542#define UVD_JPEG_POWER_STATUS__JPEG_PG_MODE__SHIFT 0x4 1543#define UVD_JPEG_POWER_STATUS__JRBC_DEC_SNOOP_DIS__SHIFT 0x8 1544#define UVD_JPEG_POWER_STATUS__JRBC_ENC_SNOOP_DIS__SHIFT 0x9 1545#define UVD_JPEG_POWER_STATUS__STALL_JDPG_POWER_UP__SHIFT 0x1f 1546#define UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK 0x00000001L 1547#define UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK 0x00000010L 1548#define UVD_JPEG_POWER_STATUS__JRBC_DEC_SNOOP_DIS_MASK 0x00000100L 1549#define UVD_JPEG_POWER_STATUS__JRBC_ENC_SNOOP_DIS_MASK 0x00000200L 1550#define UVD_JPEG_POWER_STATUS__STALL_JDPG_POWER_UP_MASK 0x80000000L 1551//UVD_DPG_LMA_CTL 1552#define UVD_DPG_LMA_CTL__READ_WRITE__SHIFT 0x0 1553#define UVD_DPG_LMA_CTL__MASK_EN__SHIFT 0x1 1554#define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT__SHIFT 0x2 1555#define UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT 0x4 1556#define UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT 0x10 1557#define UVD_DPG_LMA_CTL__READ_WRITE_MASK 0x00000001L 1558#define UVD_DPG_LMA_CTL__MASK_EN_MASK 0x00000002L 1559#define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT_MASK 0x00000004L 1560#define UVD_DPG_LMA_CTL__SRAM_SEL_MASK 0x00000010L 1561#define UVD_DPG_LMA_CTL__READ_WRITE_ADDR_MASK 0xFFFF0000L 1562//UVD_DPG_LMA_DATA 1563#define UVD_DPG_LMA_DATA__LMA_DATA__SHIFT 0x0 1564#define UVD_DPG_LMA_DATA__LMA_DATA_MASK 0xFFFFFFFFL 1565//UVD_DPG_LMA_MASK 1566#define UVD_DPG_LMA_MASK__LMA_MASK__SHIFT 0x0 1567#define UVD_DPG_LMA_MASK__LMA_MASK_MASK 0xFFFFFFFFL 1568//UVD_DPG_PAUSE 1569#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ__SHIFT 0x0 1570#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK__SHIFT 0x1 1571#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ__SHIFT 0x2 1572#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK__SHIFT 0x3 1573#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK 0x00000001L 1574#define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK 0x00000002L 1575#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK 0x00000004L 1576#define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK 0x00000008L 1577//UVD_SCRATCH1 1578#define UVD_SCRATCH1__SCRATCH1_DATA__SHIFT 0x0 1579#define UVD_SCRATCH1__SCRATCH1_DATA_MASK 0xFFFFFFFFL 1580//UVD_SCRATCH2 1581#define UVD_SCRATCH2__SCRATCH2_DATA__SHIFT 0x0 1582#define UVD_SCRATCH2__SCRATCH2_DATA_MASK 0xFFFFFFFFL 1583//UVD_SCRATCH3 1584#define UVD_SCRATCH3__SCRATCH3_DATA__SHIFT 0x0 1585#define UVD_SCRATCH3__SCRATCH3_DATA_MASK 0xFFFFFFFFL 1586//UVD_SCRATCH4 1587#define UVD_SCRATCH4__SCRATCH4_DATA__SHIFT 0x0 1588#define UVD_SCRATCH4__SCRATCH4_DATA_MASK 0xFFFFFFFFL 1589//UVD_SCRATCH5 1590#define UVD_SCRATCH5__SCRATCH5_DATA__SHIFT 0x0 1591#define UVD_SCRATCH5__SCRATCH5_DATA_MASK 0xFFFFFFFFL 1592//UVD_SCRATCH6 1593#define UVD_SCRATCH6__SCRATCH6_DATA__SHIFT 0x0 1594#define UVD_SCRATCH6__SCRATCH6_DATA_MASK 0xFFFFFFFFL 1595//UVD_SCRATCH7 1596#define UVD_SCRATCH7__SCRATCH7_DATA__SHIFT 0x0 1597#define UVD_SCRATCH7__SCRATCH7_DATA_MASK 0xFFFFFFFFL 1598//UVD_SCRATCH8 1599#define UVD_SCRATCH8__SCRATCH8_DATA__SHIFT 0x0 1600#define UVD_SCRATCH8__SCRATCH8_DATA_MASK 0xFFFFFFFFL 1601//UVD_SCRATCH9 1602#define UVD_SCRATCH9__SCRATCH9_DATA__SHIFT 0x0 1603#define UVD_SCRATCH9__SCRATCH9_DATA_MASK 0xFFFFFFFFL 1604//UVD_SCRATCH10 1605#define UVD_SCRATCH10__SCRATCH10_DATA__SHIFT 0x0 1606#define UVD_SCRATCH10__SCRATCH10_DATA_MASK 0xFFFFFFFFL 1607//UVD_SCRATCH11 1608#define UVD_SCRATCH11__SCRATCH11_DATA__SHIFT 0x0 1609#define UVD_SCRATCH11__SCRATCH11_DATA_MASK 0xFFFFFFFFL 1610//UVD_SCRATCH12 1611#define UVD_SCRATCH12__SCRATCH12_DATA__SHIFT 0x0 1612#define UVD_SCRATCH12__SCRATCH12_DATA_MASK 0xFFFFFFFFL 1613//UVD_SCRATCH13 1614#define UVD_SCRATCH13__SCRATCH13_DATA__SHIFT 0x0 1615#define UVD_SCRATCH13__SCRATCH13_DATA_MASK 0xFFFFFFFFL 1616//UVD_SCRATCH14 1617#define UVD_SCRATCH14__SCRATCH14_DATA__SHIFT 0x0 1618#define UVD_SCRATCH14__SCRATCH14_DATA_MASK 0xFFFFFFFFL 1619//UVD_FREE_COUNTER_REG 1620#define UVD_FREE_COUNTER_REG__FREE_COUNTER__SHIFT 0x0 1621#define UVD_FREE_COUNTER_REG__FREE_COUNTER_MASK 0xFFFFFFFFL 1622//UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW 1623#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 1624#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 1625//UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH 1626#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 1627#define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 1628//UVD_DPG_VCPU_CACHE_OFFSET0 1629#define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 1630#define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x01FFFFFFL 1631//UVD_DPG_LMI_VCPU_CACHE_VMID 1632#define UVD_DPG_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID__SHIFT 0x0 1633#define UVD_DPG_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID_MASK 0x0000000FL 1634//UVD_PF_STATUS 1635#define UVD_PF_STATUS__JPEG_PF_OCCURED__SHIFT 0x0 1636#define UVD_PF_STATUS__NJ_PF_OCCURED__SHIFT 0x1 1637#define UVD_PF_STATUS__ENCODER0_PF_OCCURED__SHIFT 0x2 1638#define UVD_PF_STATUS__ENCODER1_PF_OCCURED__SHIFT 0x3 1639#define UVD_PF_STATUS__ENCODER2_PF_OCCURED__SHIFT 0x4 1640#define UVD_PF_STATUS__ENCODER3_PF_OCCURED__SHIFT 0x5 1641#define UVD_PF_STATUS__ENCODER4_PF_OCCURED__SHIFT 0x6 1642#define UVD_PF_STATUS__EJPEG_PF_OCCURED__SHIFT 0x7 1643#define UVD_PF_STATUS__JPEG_PF_CLEAR__SHIFT 0x8 1644#define UVD_PF_STATUS__NJ_PF_CLEAR__SHIFT 0x9 1645#define UVD_PF_STATUS__ENCODER0_PF_CLEAR__SHIFT 0xa 1646#define UVD_PF_STATUS__ENCODER1_PF_CLEAR__SHIFT 0xb 1647#define UVD_PF_STATUS__ENCODER2_PF_CLEAR__SHIFT 0xc 1648#define UVD_PF_STATUS__ENCODER3_PF_CLEAR__SHIFT 0xd 1649#define UVD_PF_STATUS__ENCODER4_PF_CLEAR__SHIFT 0xe 1650#define UVD_PF_STATUS__EJPEG_PF_CLEAR__SHIFT 0xf 1651#define UVD_PF_STATUS__NJ_ATM_PF_OCCURED__SHIFT 0x10 1652#define UVD_PF_STATUS__DJ_ATM_PF_OCCURED__SHIFT 0x11 1653#define UVD_PF_STATUS__EJ_ATM_PF_OCCURED__SHIFT 0x12 1654#define UVD_PF_STATUS__JPEG_PF_OCCURED_MASK 0x00000001L 1655#define UVD_PF_STATUS__NJ_PF_OCCURED_MASK 0x00000002L 1656#define UVD_PF_STATUS__ENCODER0_PF_OCCURED_MASK 0x00000004L 1657#define UVD_PF_STATUS__ENCODER1_PF_OCCURED_MASK 0x00000008L 1658#define UVD_PF_STATUS__ENCODER2_PF_OCCURED_MASK 0x00000010L 1659#define UVD_PF_STATUS__ENCODER3_PF_OCCURED_MASK 0x00000020L 1660#define UVD_PF_STATUS__ENCODER4_PF_OCCURED_MASK 0x00000040L 1661#define UVD_PF_STATUS__EJPEG_PF_OCCURED_MASK 0x00000080L 1662#define UVD_PF_STATUS__JPEG_PF_CLEAR_MASK 0x00000100L 1663#define UVD_PF_STATUS__NJ_PF_CLEAR_MASK 0x00000200L 1664#define UVD_PF_STATUS__ENCODER0_PF_CLEAR_MASK 0x00000400L 1665#define UVD_PF_STATUS__ENCODER1_PF_CLEAR_MASK 0x00000800L 1666#define UVD_PF_STATUS__ENCODER2_PF_CLEAR_MASK 0x00001000L 1667#define UVD_PF_STATUS__ENCODER3_PF_CLEAR_MASK 0x00002000L 1668#define UVD_PF_STATUS__ENCODER4_PF_CLEAR_MASK 0x00004000L 1669#define UVD_PF_STATUS__EJPEG_PF_CLEAR_MASK 0x00008000L 1670#define UVD_PF_STATUS__NJ_ATM_PF_OCCURED_MASK 0x00010000L 1671#define UVD_PF_STATUS__DJ_ATM_PF_OCCURED_MASK 0x00020000L 1672#define UVD_PF_STATUS__EJ_ATM_PF_OCCURED_MASK 0x00040000L 1673//UVD_DPG_CLK_EN_VCPU_REPORT 1674#define UVD_DPG_CLK_EN_VCPU_REPORT__CLK_EN__SHIFT 0x0 1675#define UVD_DPG_CLK_EN_VCPU_REPORT__VCPU_REPORT__SHIFT 0x1 1676#define UVD_DPG_CLK_EN_VCPU_REPORT__CLK_EN_MASK 0x00000001L 1677#define UVD_DPG_CLK_EN_VCPU_REPORT__VCPU_REPORT_MASK 0x000000FEL 1678//UVD_GFX8_ADDR_CONFIG 1679#define UVD_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 1680#define UVD_GFX8_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L 1681//UVD_GFX10_ADDR_CONFIG 1682#define UVD_GFX10_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 1683#define UVD_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 1684#define UVD_GFX10_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 1685#define UVD_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 1686#define UVD_GFX10_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 1687#define UVD_GFX10_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 1688#define UVD_GFX10_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 1689#define UVD_GFX10_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 1690//UVD_GPCNT2_CNTL 1691#define UVD_GPCNT2_CNTL__CLR__SHIFT 0x0 1692#define UVD_GPCNT2_CNTL__START__SHIFT 0x1 1693#define UVD_GPCNT2_CNTL__COUNTUP__SHIFT 0x2 1694#define UVD_GPCNT2_CNTL__CLR_MASK 0x00000001L 1695#define UVD_GPCNT2_CNTL__START_MASK 0x00000002L 1696#define UVD_GPCNT2_CNTL__COUNTUP_MASK 0x00000004L 1697//UVD_GPCNT2_TARGET_LOWER 1698#define UVD_GPCNT2_TARGET_LOWER__TARGET__SHIFT 0x0 1699#define UVD_GPCNT2_TARGET_LOWER__TARGET_MASK 0xFFFFFFFFL 1700//UVD_GPCNT2_STATUS_LOWER 1701#define UVD_GPCNT2_STATUS_LOWER__COUNT__SHIFT 0x0 1702#define UVD_GPCNT2_STATUS_LOWER__COUNT_MASK 0xFFFFFFFFL 1703//UVD_GPCNT2_TARGET_UPPER 1704#define UVD_GPCNT2_TARGET_UPPER__TARGET__SHIFT 0x0 1705#define UVD_GPCNT2_TARGET_UPPER__TARGET_MASK 0x0000FFFFL 1706//UVD_GPCNT2_STATUS_UPPER 1707#define UVD_GPCNT2_STATUS_UPPER__COUNT__SHIFT 0x0 1708#define UVD_GPCNT2_STATUS_UPPER__COUNT_MASK 0x0000FFFFL 1709//UVD_GPCNT3_CNTL 1710#define UVD_GPCNT3_CNTL__CLR__SHIFT 0x0 1711#define UVD_GPCNT3_CNTL__START__SHIFT 0x1 1712#define UVD_GPCNT3_CNTL__COUNTUP__SHIFT 0x2 1713#define UVD_GPCNT3_CNTL__FREQ__SHIFT 0x3 1714#define UVD_GPCNT3_CNTL__DIV__SHIFT 0xa 1715#define UVD_GPCNT3_CNTL__CLR_MASK 0x00000001L 1716#define UVD_GPCNT3_CNTL__START_MASK 0x00000002L 1717#define UVD_GPCNT3_CNTL__COUNTUP_MASK 0x00000004L 1718#define UVD_GPCNT3_CNTL__FREQ_MASK 0x000003F8L 1719#define UVD_GPCNT3_CNTL__DIV_MASK 0x0001FC00L 1720//UVD_GPCNT3_TARGET_LOWER 1721#define UVD_GPCNT3_TARGET_LOWER__TARGET__SHIFT 0x0 1722#define UVD_GPCNT3_TARGET_LOWER__TARGET_MASK 0xFFFFFFFFL 1723//UVD_GPCNT3_STATUS_LOWER 1724#define UVD_GPCNT3_STATUS_LOWER__COUNT__SHIFT 0x0 1725#define UVD_GPCNT3_STATUS_LOWER__COUNT_MASK 0xFFFFFFFFL 1726//UVD_GPCNT3_TARGET_UPPER 1727#define UVD_GPCNT3_TARGET_UPPER__TARGET__SHIFT 0x0 1728#define UVD_GPCNT3_TARGET_UPPER__TARGET_MASK 0x0000FFFFL 1729//UVD_GPCNT3_STATUS_UPPER 1730#define UVD_GPCNT3_STATUS_UPPER__COUNT__SHIFT 0x0 1731#define UVD_GPCNT3_STATUS_UPPER__COUNT_MASK 0x0000FFFFL 1732 1733 1734// addressBlock: uvd0_uvddec 1735//UVD_STATUS 1736#define UVD_STATUS__RBC_BUSY__SHIFT 0x0 1737#define UVD_STATUS__VCPU_REPORT__SHIFT 0x1 1738#define UVD_STATUS__RBC_ACCESS_GPCOM__SHIFT 0x10 1739#define UVD_STATUS__SYS_GPCOM_REQ__SHIFT 0x1f 1740#define UVD_STATUS__RBC_BUSY_MASK 0x00000001L 1741#define UVD_STATUS__VCPU_REPORT_MASK 0x000000FEL 1742#define UVD_STATUS__RBC_ACCESS_GPCOM_MASK 0x00010000L 1743#define UVD_STATUS__SYS_GPCOM_REQ_MASK 0x80000000L 1744//UVD_ENC_PIPE_BUSY 1745#define UVD_ENC_PIPE_BUSY__IME_BUSY__SHIFT 0x0 1746#define UVD_ENC_PIPE_BUSY__SMP_BUSY__SHIFT 0x1 1747#define UVD_ENC_PIPE_BUSY__SIT_BUSY__SHIFT 0x2 1748#define UVD_ENC_PIPE_BUSY__SDB_BUSY__SHIFT 0x3 1749#define UVD_ENC_PIPE_BUSY__ENT_BUSY__SHIFT 0x4 1750#define UVD_ENC_PIPE_BUSY__ENT_HEADER_BUSY__SHIFT 0x5 1751#define UVD_ENC_PIPE_BUSY__LCM_BUSY__SHIFT 0x6 1752#define UVD_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY__SHIFT 0x7 1753#define UVD_ENC_PIPE_BUSY__MDM_RD_REF_BUSY__SHIFT 0x8 1754#define UVD_ENC_PIPE_BUSY__MDM_RD_GEN_BUSY__SHIFT 0x9 1755#define UVD_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY__SHIFT 0xa 1756#define UVD_ENC_PIPE_BUSY__MDM_WR_GEN_BUSY__SHIFT 0xb 1757#define UVD_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY__SHIFT 0x10 1758#define UVD_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY__SHIFT 0x11 1759#define UVD_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY__SHIFT 0x12 1760#define UVD_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY__SHIFT 0x13 1761#define UVD_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY__SHIFT 0x14 1762#define UVD_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY__SHIFT 0x15 1763#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY__SHIFT 0x16 1764#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY__SHIFT 0x17 1765#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY__SHIFT 0x18 1766#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY__SHIFT 0x19 1767#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY__SHIFT 0x1a 1768#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY__SHIFT 0x1b 1769#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY__SHIFT 0x1c 1770#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP2_BUSY__SHIFT 0x1d 1771#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP3_BUSY__SHIFT 0x1e 1772#define UVD_ENC_PIPE_BUSY__IME_BUSY_MASK 0x00000001L 1773#define UVD_ENC_PIPE_BUSY__SMP_BUSY_MASK 0x00000002L 1774#define UVD_ENC_PIPE_BUSY__SIT_BUSY_MASK 0x00000004L 1775#define UVD_ENC_PIPE_BUSY__SDB_BUSY_MASK 0x00000008L 1776#define UVD_ENC_PIPE_BUSY__ENT_BUSY_MASK 0x00000010L 1777#define UVD_ENC_PIPE_BUSY__ENT_HEADER_BUSY_MASK 0x00000020L 1778#define UVD_ENC_PIPE_BUSY__LCM_BUSY_MASK 0x00000040L 1779#define UVD_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY_MASK 0x00000080L 1780#define UVD_ENC_PIPE_BUSY__MDM_RD_REF_BUSY_MASK 0x00000100L 1781#define UVD_ENC_PIPE_BUSY__MDM_RD_GEN_BUSY_MASK 0x00000200L 1782#define UVD_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY_MASK 0x00000400L 1783#define UVD_ENC_PIPE_BUSY__MDM_WR_GEN_BUSY_MASK 0x00000800L 1784#define UVD_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY_MASK 0x00010000L 1785#define UVD_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY_MASK 0x00020000L 1786#define UVD_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY_MASK 0x00040000L 1787#define UVD_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY_MASK 0x00080000L 1788#define UVD_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY_MASK 0x00100000L 1789#define UVD_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY_MASK 0x00200000L 1790#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY_MASK 0x00400000L 1791#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY_MASK 0x00800000L 1792#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY_MASK 0x01000000L 1793#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY_MASK 0x02000000L 1794#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY_MASK 0x04000000L 1795#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY_MASK 0x08000000L 1796#define UVD_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY_MASK 0x10000000L 1797#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP2_BUSY_MASK 0x20000000L 1798#define UVD_ENC_PIPE_BUSY__MIF_WR_BSP3_BUSY_MASK 0x40000000L 1799//UVD_SOFT_RESET 1800#define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x0 1801#define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x1 1802#define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x2 1803#define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT 0x3 1804#define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT 0x4 1805#define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT 0x6 1806#define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x7 1807#define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x8 1808#define UVD_SOFT_RESET__EFC_SOFT_RESET__SHIFT 0x9 1809#define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa 1810#define UVD_SOFT_RESET__MPRD_SOFT_RESET__SHIFT 0xb 1811#define UVD_SOFT_RESET__IDCT_SOFT_RESET__SHIFT 0xc 1812#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0xd 1813#define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0xe 1814#define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0xf 1815#define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x10 1816#define UVD_SOFT_RESET__SUVD_SOFT_RESET__SHIFT 0x11 1817#define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS__SHIFT 0x12 1818#define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS__SHIFT 0x13 1819#define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS__SHIFT 0x14 1820#define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS__SHIFT 0x15 1821#define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS__SHIFT 0x16 1822#define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS__SHIFT 0x17 1823#define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS__SHIFT 0x18 1824#define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS__SHIFT 0x19 1825#define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS__SHIFT 0x1a 1826#define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS__SHIFT 0x1b 1827#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS__SHIFT 0x1c 1828#define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS__SHIFT 0x1d 1829#define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS__SHIFT 0x1e 1830#define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS__SHIFT 0x1f 1831#define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK 0x00000001L 1832#define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x00000002L 1833#define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK 0x00000004L 1834#define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK 0x00000008L 1835#define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK 0x00000010L 1836#define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK 0x00000040L 1837#define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00000080L 1838#define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x00000100L 1839#define UVD_SOFT_RESET__EFC_SOFT_RESET_MASK 0x00000200L 1840#define UVD_SOFT_RESET__IH_SOFT_RESET_MASK 0x00000400L 1841#define UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK 0x00000800L 1842#define UVD_SOFT_RESET__IDCT_SOFT_RESET_MASK 0x00001000L 1843#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x00002000L 1844#define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK 0x00004000L 1845#define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK 0x00008000L 1846#define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK 0x00010000L 1847#define UVD_SOFT_RESET__SUVD_SOFT_RESET_MASK 0x00020000L 1848#define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS_MASK 0x00040000L 1849#define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS_MASK 0x00080000L 1850#define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS_MASK 0x00100000L 1851#define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS_MASK 0x00200000L 1852#define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS_MASK 0x00400000L 1853#define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS_MASK 0x00800000L 1854#define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS_MASK 0x01000000L 1855#define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS_MASK 0x02000000L 1856#define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS_MASK 0x04000000L 1857#define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS_MASK 0x08000000L 1858#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK 0x10000000L 1859#define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS_MASK 0x20000000L 1860#define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS_MASK 0x40000000L 1861#define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS_MASK 0x80000000L 1862//UVD_SOFT_RESET2 1863#define UVD_SOFT_RESET2__ATOMIC_SOFT_RESET__SHIFT 0x0 1864#define UVD_SOFT_RESET2__MMSCH_VCLK_RESET_STATUS__SHIFT 0x10 1865#define UVD_SOFT_RESET2__MMSCH_SCLK_RESET_STATUS__SHIFT 0x11 1866#define UVD_SOFT_RESET2__ATOMIC_SOFT_RESET_MASK 0x00000001L 1867#define UVD_SOFT_RESET2__MMSCH_VCLK_RESET_STATUS_MASK 0x00010000L 1868#define UVD_SOFT_RESET2__MMSCH_SCLK_RESET_STATUS_MASK 0x00020000L 1869//UVD_MMSCH_SOFT_RESET 1870#define UVD_MMSCH_SOFT_RESET__MMSCH_RESET__SHIFT 0x0 1871#define UVD_MMSCH_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x1 1872#define UVD_MMSCH_SOFT_RESET__MMSCH_LOCK__SHIFT 0x1f 1873#define UVD_MMSCH_SOFT_RESET__MMSCH_RESET_MASK 0x00000001L 1874#define UVD_MMSCH_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00000002L 1875#define UVD_MMSCH_SOFT_RESET__MMSCH_LOCK_MASK 0x80000000L 1876//UVD_CGC_GATE 1877#define UVD_CGC_GATE__SYS__SHIFT 0x0 1878#define UVD_CGC_GATE__UDEC__SHIFT 0x1 1879#define UVD_CGC_GATE__MPEG2__SHIFT 0x2 1880#define UVD_CGC_GATE__REGS__SHIFT 0x3 1881#define UVD_CGC_GATE__RBC__SHIFT 0x4 1882#define UVD_CGC_GATE__LMI_MC__SHIFT 0x5 1883#define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6 1884#define UVD_CGC_GATE__IDCT__SHIFT 0x7 1885#define UVD_CGC_GATE__MPRD__SHIFT 0x8 1886#define UVD_CGC_GATE__MPC__SHIFT 0x9 1887#define UVD_CGC_GATE__LBSI__SHIFT 0xa 1888#define UVD_CGC_GATE__LRBBM__SHIFT 0xb 1889#define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc 1890#define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd 1891#define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe 1892#define UVD_CGC_GATE__UDEC_DB__SHIFT 0xf 1893#define UVD_CGC_GATE__UDEC_MP__SHIFT 0x10 1894#define UVD_CGC_GATE__WCB__SHIFT 0x11 1895#define UVD_CGC_GATE__VCPU__SHIFT 0x12 1896#define UVD_CGC_GATE__MMSCH__SHIFT 0x14 1897#define UVD_CGC_GATE__SYS_MASK 0x00000001L 1898#define UVD_CGC_GATE__UDEC_MASK 0x00000002L 1899#define UVD_CGC_GATE__MPEG2_MASK 0x00000004L 1900#define UVD_CGC_GATE__REGS_MASK 0x00000008L 1901#define UVD_CGC_GATE__RBC_MASK 0x00000010L 1902#define UVD_CGC_GATE__LMI_MC_MASK 0x00000020L 1903#define UVD_CGC_GATE__LMI_UMC_MASK 0x00000040L 1904#define UVD_CGC_GATE__IDCT_MASK 0x00000080L 1905#define UVD_CGC_GATE__MPRD_MASK 0x00000100L 1906#define UVD_CGC_GATE__MPC_MASK 0x00000200L 1907#define UVD_CGC_GATE__LBSI_MASK 0x00000400L 1908#define UVD_CGC_GATE__LRBBM_MASK 0x00000800L 1909#define UVD_CGC_GATE__UDEC_RE_MASK 0x00001000L 1910#define UVD_CGC_GATE__UDEC_CM_MASK 0x00002000L 1911#define UVD_CGC_GATE__UDEC_IT_MASK 0x00004000L 1912#define UVD_CGC_GATE__UDEC_DB_MASK 0x00008000L 1913#define UVD_CGC_GATE__UDEC_MP_MASK 0x00010000L 1914#define UVD_CGC_GATE__WCB_MASK 0x00020000L 1915#define UVD_CGC_GATE__VCPU_MASK 0x00040000L 1916#define UVD_CGC_GATE__MMSCH_MASK 0x00100000L 1917//UVD_CGC_STATUS 1918#define UVD_CGC_STATUS__SYS_SCLK__SHIFT 0x0 1919#define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x1 1920#define UVD_CGC_STATUS__SYS_VCLK__SHIFT 0x2 1921#define UVD_CGC_STATUS__UDEC_SCLK__SHIFT 0x3 1922#define UVD_CGC_STATUS__UDEC_DCLK__SHIFT 0x4 1923#define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x5 1924#define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x6 1925#define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x7 1926#define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x8 1927#define UVD_CGC_STATUS__REGS_SCLK__SHIFT 0x9 1928#define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0xa 1929#define UVD_CGC_STATUS__RBC_SCLK__SHIFT 0xb 1930#define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0xc 1931#define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0xd 1932#define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0xe 1933#define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0xf 1934#define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x10 1935#define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x11 1936#define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x12 1937#define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x13 1938#define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14 1939#define UVD_CGC_STATUS__LBSI_SCLK__SHIFT 0x15 1940#define UVD_CGC_STATUS__LBSI_VCLK__SHIFT 0x16 1941#define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x17 1942#define UVD_CGC_STATUS__WCB_SCLK__SHIFT 0x18 1943#define UVD_CGC_STATUS__VCPU_SCLK__SHIFT 0x19 1944#define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x1a 1945#define UVD_CGC_STATUS__MMSCH_SCLK__SHIFT 0x1b 1946#define UVD_CGC_STATUS__MMSCH_VCLK__SHIFT 0x1c 1947#define UVD_CGC_STATUS__ALL_ENC_ACTIVE__SHIFT 0x1d 1948#define UVD_CGC_STATUS__ALL_DEC_ACTIVE__SHIFT 0x1f 1949#define UVD_CGC_STATUS__SYS_SCLK_MASK 0x00000001L 1950#define UVD_CGC_STATUS__SYS_DCLK_MASK 0x00000002L 1951#define UVD_CGC_STATUS__SYS_VCLK_MASK 0x00000004L 1952#define UVD_CGC_STATUS__UDEC_SCLK_MASK 0x00000008L 1953#define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x00000010L 1954#define UVD_CGC_STATUS__UDEC_VCLK_MASK 0x00000020L 1955#define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x00000040L 1956#define UVD_CGC_STATUS__MPEG2_DCLK_MASK 0x00000080L 1957#define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x00000100L 1958#define UVD_CGC_STATUS__REGS_SCLK_MASK 0x00000200L 1959#define UVD_CGC_STATUS__REGS_VCLK_MASK 0x00000400L 1960#define UVD_CGC_STATUS__RBC_SCLK_MASK 0x00000800L 1961#define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x00001000L 1962#define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK 0x00002000L 1963#define UVD_CGC_STATUS__IDCT_SCLK_MASK 0x00004000L 1964#define UVD_CGC_STATUS__IDCT_VCLK_MASK 0x00008000L 1965#define UVD_CGC_STATUS__MPRD_SCLK_MASK 0x00010000L 1966#define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x00020000L 1967#define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x00040000L 1968#define UVD_CGC_STATUS__MPC_SCLK_MASK 0x00080000L 1969#define UVD_CGC_STATUS__MPC_DCLK_MASK 0x00100000L 1970#define UVD_CGC_STATUS__LBSI_SCLK_MASK 0x00200000L 1971#define UVD_CGC_STATUS__LBSI_VCLK_MASK 0x00400000L 1972#define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x00800000L 1973#define UVD_CGC_STATUS__WCB_SCLK_MASK 0x01000000L 1974#define UVD_CGC_STATUS__VCPU_SCLK_MASK 0x02000000L 1975#define UVD_CGC_STATUS__VCPU_VCLK_MASK 0x04000000L 1976#define UVD_CGC_STATUS__MMSCH_SCLK_MASK 0x08000000L 1977#define UVD_CGC_STATUS__MMSCH_VCLK_MASK 0x10000000L 1978#define UVD_CGC_STATUS__ALL_ENC_ACTIVE_MASK 0x20000000L 1979#define UVD_CGC_STATUS__ALL_DEC_ACTIVE_MASK 0x80000000L 1980//UVD_CGC_CTRL 1981#define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 1982#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2 1983#define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6 1984#define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb 1985#define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc 1986#define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd 1987#define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0xe 1988#define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf 1989#define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10 1990#define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11 1991#define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12 1992#define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13 1993#define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14 1994#define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15 1995#define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16 1996#define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17 1997#define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18 1998#define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x19 1999#define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a 2000#define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x1b 2001#define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c 2002#define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x1d 2003#define UVD_CGC_CTRL__MMSCH_MODE__SHIFT 0x1f 2004#define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L 2005#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003CL 2006#define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007C0L 2007#define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x00000800L 2008#define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x00001000L 2009#define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x00002000L 2010#define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x00004000L 2011#define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x00008000L 2012#define UVD_CGC_CTRL__SYS_MODE_MASK 0x00010000L 2013#define UVD_CGC_CTRL__UDEC_MODE_MASK 0x00020000L 2014#define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x00040000L 2015#define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L 2016#define UVD_CGC_CTRL__RBC_MODE_MASK 0x00100000L 2017#define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x00200000L 2018#define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x00400000L 2019#define UVD_CGC_CTRL__IDCT_MODE_MASK 0x00800000L 2020#define UVD_CGC_CTRL__MPRD_MODE_MASK 0x01000000L 2021#define UVD_CGC_CTRL__MPC_MODE_MASK 0x02000000L 2022#define UVD_CGC_CTRL__LBSI_MODE_MASK 0x04000000L 2023#define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x08000000L 2024#define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000L 2025#define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000L 2026#define UVD_CGC_CTRL__MMSCH_MODE_MASK 0x80000000L 2027//UVD_CGC_UDEC_STATUS 2028#define UVD_CGC_UDEC_STATUS__RE_SCLK__SHIFT 0x0 2029#define UVD_CGC_UDEC_STATUS__RE_DCLK__SHIFT 0x1 2030#define UVD_CGC_UDEC_STATUS__RE_VCLK__SHIFT 0x2 2031#define UVD_CGC_UDEC_STATUS__CM_SCLK__SHIFT 0x3 2032#define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT 0x4 2033#define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5 2034#define UVD_CGC_UDEC_STATUS__IT_SCLK__SHIFT 0x6 2035#define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT 0x7 2036#define UVD_CGC_UDEC_STATUS__IT_VCLK__SHIFT 0x8 2037#define UVD_CGC_UDEC_STATUS__DB_SCLK__SHIFT 0x9 2038#define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT 0xa 2039#define UVD_CGC_UDEC_STATUS__DB_VCLK__SHIFT 0xb 2040#define UVD_CGC_UDEC_STATUS__MP_SCLK__SHIFT 0xc 2041#define UVD_CGC_UDEC_STATUS__MP_DCLK__SHIFT 0xd 2042#define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe 2043#define UVD_CGC_UDEC_STATUS__RE_SCLK_MASK 0x00000001L 2044#define UVD_CGC_UDEC_STATUS__RE_DCLK_MASK 0x00000002L 2045#define UVD_CGC_UDEC_STATUS__RE_VCLK_MASK 0x00000004L 2046#define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK 0x00000008L 2047#define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x00000010L 2048#define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x00000020L 2049#define UVD_CGC_UDEC_STATUS__IT_SCLK_MASK 0x00000040L 2050#define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 0x00000080L 2051#define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x00000100L 2052#define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK 0x00000200L 2053#define UVD_CGC_UDEC_STATUS__DB_DCLK_MASK 0x00000400L 2054#define UVD_CGC_UDEC_STATUS__DB_VCLK_MASK 0x00000800L 2055#define UVD_CGC_UDEC_STATUS__MP_SCLK_MASK 0x00001000L 2056#define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x00002000L 2057#define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK 0x00004000L 2058//UVD_SUVD_CGC_GATE 2059#define UVD_SUVD_CGC_GATE__SRE__SHIFT 0x0 2060#define UVD_SUVD_CGC_GATE__SIT__SHIFT 0x1 2061#define UVD_SUVD_CGC_GATE__SMP__SHIFT 0x2 2062#define UVD_SUVD_CGC_GATE__SCM__SHIFT 0x3 2063#define UVD_SUVD_CGC_GATE__SDB__SHIFT 0x4 2064#define UVD_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 2065#define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 2066#define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 2067#define UVD_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 2068#define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 2069#define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 2070#define UVD_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 2071#define UVD_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 2072#define UVD_SUVD_CGC_GATE__SCLR__SHIFT 0xd 2073#define UVD_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 2074#define UVD_SUVD_CGC_GATE__ENT__SHIFT 0xf 2075#define UVD_SUVD_CGC_GATE__IME__SHIFT 0x10 2076#define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 2077#define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 2078#define UVD_SUVD_CGC_GATE__SITE__SHIFT 0x13 2079#define UVD_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 2080#define UVD_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 2081#define UVD_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 2082#define UVD_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 2083#define UVD_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 2084#define UVD_SUVD_CGC_GATE__EFC__SHIFT 0x19 2085#define UVD_SUVD_CGC_GATE__SRE_MASK 0x00000001L 2086#define UVD_SUVD_CGC_GATE__SIT_MASK 0x00000002L 2087#define UVD_SUVD_CGC_GATE__SMP_MASK 0x00000004L 2088#define UVD_SUVD_CGC_GATE__SCM_MASK 0x00000008L 2089#define UVD_SUVD_CGC_GATE__SDB_MASK 0x00000010L 2090#define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 2091#define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 2092#define UVD_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 2093#define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 2094#define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 2095#define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 2096#define UVD_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 2097#define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 2098#define UVD_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 2099#define UVD_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 2100#define UVD_SUVD_CGC_GATE__ENT_MASK 0x00008000L 2101#define UVD_SUVD_CGC_GATE__IME_MASK 0x00010000L 2102#define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 2103#define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 2104#define UVD_SUVD_CGC_GATE__SITE_MASK 0x00080000L 2105#define UVD_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 2106#define UVD_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 2107#define UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 2108#define UVD_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 2109#define UVD_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 2110#define UVD_SUVD_CGC_GATE__EFC_MASK 0x02000000L 2111//UVD_SUVD_CGC_STATUS 2112#define UVD_SUVD_CGC_STATUS__SRE_VCLK__SHIFT 0x0 2113#define UVD_SUVD_CGC_STATUS__SRE_DCLK__SHIFT 0x1 2114#define UVD_SUVD_CGC_STATUS__SIT_DCLK__SHIFT 0x2 2115#define UVD_SUVD_CGC_STATUS__SMP_DCLK__SHIFT 0x3 2116#define UVD_SUVD_CGC_STATUS__SCM_DCLK__SHIFT 0x4 2117#define UVD_SUVD_CGC_STATUS__SDB_DCLK__SHIFT 0x5 2118#define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT 0x6 2119#define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK__SHIFT 0x7 2120#define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK__SHIFT 0x8 2121#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK__SHIFT 0x9 2122#define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK__SHIFT 0xa 2123#define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT 0xb 2124#define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK__SHIFT 0xc 2125#define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK__SHIFT 0xd 2126#define UVD_SUVD_CGC_STATUS__SCLR_DCLK__SHIFT 0xe 2127#define UVD_SUVD_CGC_STATUS__UVD_SC__SHIFT 0xf 2128#define UVD_SUVD_CGC_STATUS__ENT_DCLK__SHIFT 0x10 2129#define UVD_SUVD_CGC_STATUS__IME_DCLK__SHIFT 0x11 2130#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK__SHIFT 0x12 2131#define UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK__SHIFT 0x13 2132#define UVD_SUVD_CGC_STATUS__SITE_DCLK__SHIFT 0x14 2133#define UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK__SHIFT 0x15 2134#define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK__SHIFT 0x16 2135#define UVD_SUVD_CGC_STATUS__SRE_VP9_VCLK__SHIFT 0x17 2136#define UVD_SUVD_CGC_STATUS__SCM_VP9_VCLK__SHIFT 0x18 2137#define UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK__SHIFT 0x19 2138#define UVD_SUVD_CGC_STATUS__SDB_VP9_DCLK__SHIFT 0x1a 2139#define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK__SHIFT 0x1b 2140#define UVD_SUVD_CGC_STATUS__EFC_DCLK__SHIFT 0x1c 2141#define UVD_SUVD_CGC_STATUS__SRE_VCLK_MASK 0x00000001L 2142#define UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK 0x00000002L 2143#define UVD_SUVD_CGC_STATUS__SIT_DCLK_MASK 0x00000004L 2144#define UVD_SUVD_CGC_STATUS__SMP_DCLK_MASK 0x00000008L 2145#define UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK 0x00000010L 2146#define UVD_SUVD_CGC_STATUS__SDB_DCLK_MASK 0x00000020L 2147#define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK 0x00000040L 2148#define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x00000080L 2149#define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK_MASK 0x00000100L 2150#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK 0x00000200L 2151#define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK_MASK 0x00000400L 2152#define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK 0x00000800L 2153#define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK_MASK 0x00001000L 2154#define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK_MASK 0x00002000L 2155#define UVD_SUVD_CGC_STATUS__SCLR_DCLK_MASK 0x00004000L 2156#define UVD_SUVD_CGC_STATUS__UVD_SC_MASK 0x00008000L 2157#define UVD_SUVD_CGC_STATUS__ENT_DCLK_MASK 0x00010000L 2158#define UVD_SUVD_CGC_STATUS__IME_DCLK_MASK 0x00020000L 2159#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK_MASK 0x00040000L 2160#define UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK_MASK 0x00080000L 2161#define UVD_SUVD_CGC_STATUS__SITE_DCLK_MASK 0x00100000L 2162#define UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK_MASK 0x00200000L 2163#define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK_MASK 0x00400000L 2164#define UVD_SUVD_CGC_STATUS__SRE_VP9_VCLK_MASK 0x00800000L 2165#define UVD_SUVD_CGC_STATUS__SCM_VP9_VCLK_MASK 0x01000000L 2166#define UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK_MASK 0x02000000L 2167#define UVD_SUVD_CGC_STATUS__SDB_VP9_DCLK_MASK 0x04000000L 2168#define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK_MASK 0x08000000L 2169#define UVD_SUVD_CGC_STATUS__EFC_DCLK_MASK 0x10000000L 2170//UVD_SUVD_CGC_CTRL 2171#define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 2172#define UVD_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 2173#define UVD_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 2174#define UVD_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 2175#define UVD_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 2176#define UVD_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 2177#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 2178#define UVD_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 2179#define UVD_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 2180#define UVD_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 2181#define UVD_SUVD_CGC_CTRL__EFC_MODE__SHIFT 0xa 2182#define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 2183#define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 2184#define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 2185#define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 2186#define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 2187#define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 2188#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 2189#define UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 2190#define UVD_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 2191#define UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 2192#define UVD_SUVD_CGC_CTRL__EFC_MODE_MASK 0x00000400L 2193//UVD_GPCOM_VCPU_CMD 2194#define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0 2195#define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1 2196#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x1f 2197#define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x00000001L 2198#define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7FFFFFFEL 2199#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000L 2200//UVD_GPCOM_VCPU_DATA0 2201#define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0 2202#define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xFFFFFFFFL 2203//UVD_GPCOM_VCPU_DATA1 2204#define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0 2205#define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xFFFFFFFFL 2206//UVD_GPCOM_SYS_CMD 2207#define UVD_GPCOM_SYS_CMD__CMD_SEND__SHIFT 0x0 2208#define UVD_GPCOM_SYS_CMD__CMD__SHIFT 0x1 2209#define UVD_GPCOM_SYS_CMD__CMD_SOURCE__SHIFT 0x1f 2210#define UVD_GPCOM_SYS_CMD__CMD_SEND_MASK 0x00000001L 2211#define UVD_GPCOM_SYS_CMD__CMD_MASK 0x7FFFFFFEL 2212#define UVD_GPCOM_SYS_CMD__CMD_SOURCE_MASK 0x80000000L 2213//UVD_GPCOM_SYS_DATA0 2214#define UVD_GPCOM_SYS_DATA0__DATA0__SHIFT 0x0 2215#define UVD_GPCOM_SYS_DATA0__DATA0_MASK 0xFFFFFFFFL 2216//UVD_GPCOM_SYS_DATA1 2217#define UVD_GPCOM_SYS_DATA1__DATA1__SHIFT 0x0 2218#define UVD_GPCOM_SYS_DATA1__DATA1_MASK 0xFFFFFFFFL 2219//UVD_VCPU_INT_EN 2220#define UVD_VCPU_INT_EN__PIF_ADDR_ERR_EN__SHIFT 0x0 2221#define UVD_VCPU_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN__SHIFT 0x1 2222#define UVD_VCPU_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN__SHIFT 0x2 2223#define UVD_VCPU_INT_EN__NJ_PF_RPT_EN__SHIFT 0x3 2224#define UVD_VCPU_INT_EN__SW_RB1_INT_EN__SHIFT 0x4 2225#define UVD_VCPU_INT_EN__SW_RB2_INT_EN__SHIFT 0x5 2226#define UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_EN__SHIFT 0x6 2227#define UVD_VCPU_INT_EN__SW_RB3_INT_EN__SHIFT 0x7 2228#define UVD_VCPU_INT_EN__SW_RB4_INT_EN__SHIFT 0x9 2229#define UVD_VCPU_INT_EN__SW_RB5_INT_EN__SHIFT 0xa 2230#define UVD_VCPU_INT_EN__LBSI_EN__SHIFT 0xb 2231#define UVD_VCPU_INT_EN__UDEC_EN__SHIFT 0xc 2232#define UVD_VCPU_INT_EN__RPTR_WR_EN__SHIFT 0x10 2233#define UVD_VCPU_INT_EN__JOB_START_EN__SHIFT 0x11 2234#define UVD_VCPU_INT_EN__NJ_PF_EN__SHIFT 0x12 2235#define UVD_VCPU_INT_EN__SEMA_WAIT_FAIL_SIG_EN__SHIFT 0x17 2236#define UVD_VCPU_INT_EN__IDCT_EN__SHIFT 0x18 2237#define UVD_VCPU_INT_EN__MPRD_EN__SHIFT 0x19 2238#define UVD_VCPU_INT_EN__AVM_INT_EN__SHIFT 0x1a 2239#define UVD_VCPU_INT_EN__CLK_SWT_EN__SHIFT 0x1b 2240#define UVD_VCPU_INT_EN__MIF_HWINT_EN__SHIFT 0x1c 2241#define UVD_VCPU_INT_EN__MPRD_ERR_EN__SHIFT 0x1d 2242#define UVD_VCPU_INT_EN__DRV_FW_REQ_EN__SHIFT 0x1e 2243#define UVD_VCPU_INT_EN__DRV_FW_ACK_EN__SHIFT 0x1f 2244#define UVD_VCPU_INT_EN__PIF_ADDR_ERR_EN_MASK 0x00000001L 2245#define UVD_VCPU_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN_MASK 0x00000002L 2246#define UVD_VCPU_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN_MASK 0x00000004L 2247#define UVD_VCPU_INT_EN__NJ_PF_RPT_EN_MASK 0x00000008L 2248#define UVD_VCPU_INT_EN__SW_RB1_INT_EN_MASK 0x00000010L 2249#define UVD_VCPU_INT_EN__SW_RB2_INT_EN_MASK 0x00000020L 2250#define UVD_VCPU_INT_EN__RBC_REG_PRIV_FAULT_EN_MASK 0x00000040L 2251#define UVD_VCPU_INT_EN__SW_RB3_INT_EN_MASK 0x00000080L 2252#define UVD_VCPU_INT_EN__SW_RB4_INT_EN_MASK 0x00000200L 2253#define UVD_VCPU_INT_EN__SW_RB5_INT_EN_MASK 0x00000400L 2254#define UVD_VCPU_INT_EN__LBSI_EN_MASK 0x00000800L 2255#define UVD_VCPU_INT_EN__UDEC_EN_MASK 0x00001000L 2256#define UVD_VCPU_INT_EN__RPTR_WR_EN_MASK 0x00010000L 2257#define UVD_VCPU_INT_EN__JOB_START_EN_MASK 0x00020000L 2258#define UVD_VCPU_INT_EN__NJ_PF_EN_MASK 0x00040000L 2259#define UVD_VCPU_INT_EN__SEMA_WAIT_FAIL_SIG_EN_MASK 0x00800000L 2260#define UVD_VCPU_INT_EN__IDCT_EN_MASK 0x01000000L 2261#define UVD_VCPU_INT_EN__MPRD_EN_MASK 0x02000000L 2262#define UVD_VCPU_INT_EN__AVM_INT_EN_MASK 0x04000000L 2263#define UVD_VCPU_INT_EN__CLK_SWT_EN_MASK 0x08000000L 2264#define UVD_VCPU_INT_EN__MIF_HWINT_EN_MASK 0x10000000L 2265#define UVD_VCPU_INT_EN__MPRD_ERR_EN_MASK 0x20000000L 2266#define UVD_VCPU_INT_EN__DRV_FW_REQ_EN_MASK 0x40000000L 2267#define UVD_VCPU_INT_EN__DRV_FW_ACK_EN_MASK 0x80000000L 2268//UVD_VCPU_INT_ACK 2269#define UVD_VCPU_INT_ACK__PIF_ADDR_ERR_ACK__SHIFT 0x0 2270#define UVD_VCPU_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK__SHIFT 0x1 2271#define UVD_VCPU_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK__SHIFT 0x2 2272#define UVD_VCPU_INT_ACK__NJ_PF_RPT_ACK__SHIFT 0x3 2273#define UVD_VCPU_INT_ACK__SW_RB1_INT_ACK__SHIFT 0x4 2274#define UVD_VCPU_INT_ACK__SW_RB2_INT_ACK__SHIFT 0x5 2275#define UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_ACK__SHIFT 0x6 2276#define UVD_VCPU_INT_ACK__SW_RB3_INT_ACK__SHIFT 0x7 2277#define UVD_VCPU_INT_ACK__SW_RB4_INT_ACK__SHIFT 0x9 2278#define UVD_VCPU_INT_ACK__SW_RB5_INT_ACK__SHIFT 0xa 2279#define UVD_VCPU_INT_ACK__LBSI_ACK__SHIFT 0xb 2280#define UVD_VCPU_INT_ACK__UDEC_ACK__SHIFT 0xc 2281#define UVD_VCPU_INT_ACK__RPTR_WR_ACK__SHIFT 0x10 2282#define UVD_VCPU_INT_ACK__JOB_START_ACK__SHIFT 0x11 2283#define UVD_VCPU_INT_ACK__NJ_PF_ACK__SHIFT 0x12 2284#define UVD_VCPU_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK__SHIFT 0x17 2285#define UVD_VCPU_INT_ACK__IDCT_ACK__SHIFT 0x18 2286#define UVD_VCPU_INT_ACK__MPRD_ACK__SHIFT 0x19 2287#define UVD_VCPU_INT_ACK__AVM_INT_ACK__SHIFT 0x1a 2288#define UVD_VCPU_INT_ACK__CLK_SWT_ACK__SHIFT 0x1b 2289#define UVD_VCPU_INT_ACK__MIF_HWINT_ACK__SHIFT 0x1c 2290#define UVD_VCPU_INT_ACK__MPRD_ERR_ACK__SHIFT 0x1d 2291#define UVD_VCPU_INT_ACK__DRV_FW_REQ_ACK__SHIFT 0x1e 2292#define UVD_VCPU_INT_ACK__DRV_FW_ACK_ACK__SHIFT 0x1f 2293#define UVD_VCPU_INT_ACK__PIF_ADDR_ERR_ACK_MASK 0x00000001L 2294#define UVD_VCPU_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK_MASK 0x00000002L 2295#define UVD_VCPU_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK_MASK 0x00000004L 2296#define UVD_VCPU_INT_ACK__NJ_PF_RPT_ACK_MASK 0x00000008L 2297#define UVD_VCPU_INT_ACK__SW_RB1_INT_ACK_MASK 0x00000010L 2298#define UVD_VCPU_INT_ACK__SW_RB2_INT_ACK_MASK 0x00000020L 2299#define UVD_VCPU_INT_ACK__RBC_REG_PRIV_FAULT_ACK_MASK 0x00000040L 2300#define UVD_VCPU_INT_ACK__SW_RB3_INT_ACK_MASK 0x00000080L 2301#define UVD_VCPU_INT_ACK__SW_RB4_INT_ACK_MASK 0x00000200L 2302#define UVD_VCPU_INT_ACK__SW_RB5_INT_ACK_MASK 0x00000400L 2303#define UVD_VCPU_INT_ACK__LBSI_ACK_MASK 0x00000800L 2304#define UVD_VCPU_INT_ACK__UDEC_ACK_MASK 0x00001000L 2305#define UVD_VCPU_INT_ACK__RPTR_WR_ACK_MASK 0x00010000L 2306#define UVD_VCPU_INT_ACK__JOB_START_ACK_MASK 0x00020000L 2307#define UVD_VCPU_INT_ACK__NJ_PF_ACK_MASK 0x00040000L 2308#define UVD_VCPU_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK_MASK 0x00800000L 2309#define UVD_VCPU_INT_ACK__IDCT_ACK_MASK 0x01000000L 2310#define UVD_VCPU_INT_ACK__MPRD_ACK_MASK 0x02000000L 2311#define UVD_VCPU_INT_ACK__AVM_INT_ACK_MASK 0x04000000L 2312#define UVD_VCPU_INT_ACK__CLK_SWT_ACK_MASK 0x08000000L 2313#define UVD_VCPU_INT_ACK__MIF_HWINT_ACK_MASK 0x10000000L 2314#define UVD_VCPU_INT_ACK__MPRD_ERR_ACK_MASK 0x20000000L 2315#define UVD_VCPU_INT_ACK__DRV_FW_REQ_ACK_MASK 0x40000000L 2316#define UVD_VCPU_INT_ACK__DRV_FW_ACK_ACK_MASK 0x80000000L 2317//UVD_VCPU_INT_ROUTE 2318#define UVD_VCPU_INT_ROUTE__DRV_FW_MSG__SHIFT 0x0 2319#define UVD_VCPU_INT_ROUTE__FW_DRV_MSG_ACK__SHIFT 0x1 2320#define UVD_VCPU_INT_ROUTE__VCPU_GPCOM__SHIFT 0x2 2321#define UVD_VCPU_INT_ROUTE__DRV_FW_MSG_MASK 0x00000001L 2322#define UVD_VCPU_INT_ROUTE__FW_DRV_MSG_ACK_MASK 0x00000002L 2323#define UVD_VCPU_INT_ROUTE__VCPU_GPCOM_MASK 0x00000004L 2324//UVD_ENC_VCPU_INT_EN 2325#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR_EN__SHIFT 0x0 2326#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR2_EN__SHIFT 0x1 2327#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR3_EN__SHIFT 0x2 2328#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR_EN_MASK 0x00000001L 2329#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR2_EN_MASK 0x00000002L 2330#define UVD_ENC_VCPU_INT_EN__DCE_UVD_SCAN_IN_BUFMGR3_EN_MASK 0x00000004L 2331//UVD_ENC_VCPU_INT_ACK 2332#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR_ACK__SHIFT 0x0 2333#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR2_ACK__SHIFT 0x1 2334#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR3_ACK__SHIFT 0x2 2335#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR_ACK_MASK 0x00000001L 2336#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR2_ACK_MASK 0x00000002L 2337#define UVD_ENC_VCPU_INT_ACK__DCE_UVD_SCAN_IN_BUFMGR3_ACK_MASK 0x00000004L 2338//UVD_MASTINT_EN 2339#define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 2340#define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1 2341#define UVD_MASTINT_EN__SYS_EN__SHIFT 0x2 2342#define UVD_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 2343#define UVD_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L 2344#define UVD_MASTINT_EN__VCPU_EN_MASK 0x00000002L 2345#define UVD_MASTINT_EN__SYS_EN_MASK 0x00000004L 2346#define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x007FFFF0L 2347//UVD_SYS_INT_EN 2348#define UVD_SYS_INT_EN__PIF_ADDR_ERR_EN__SHIFT 0x0 2349#define UVD_SYS_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN__SHIFT 0x1 2350#define UVD_SYS_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN__SHIFT 0x2 2351#define UVD_SYS_INT_EN__CXW_WR_EN__SHIFT 0x3 2352#define UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_EN__SHIFT 0x6 2353#define UVD_SYS_INT_EN__LBSI_EN__SHIFT 0xb 2354#define UVD_SYS_INT_EN__UDEC_EN__SHIFT 0xc 2355#define UVD_SYS_INT_EN__JOB_DONE_EN__SHIFT 0x10 2356#define UVD_SYS_INT_EN__SEMA_WAIT_FAIL_SIG_EN__SHIFT 0x17 2357#define UVD_SYS_INT_EN__IDCT_EN__SHIFT 0x18 2358#define UVD_SYS_INT_EN__MPRD_EN__SHIFT 0x19 2359#define UVD_SYS_INT_EN__CLK_SWT_EN__SHIFT 0x1b 2360#define UVD_SYS_INT_EN__MIF_HWINT_EN__SHIFT 0x1c 2361#define UVD_SYS_INT_EN__MPRD_ERR_EN__SHIFT 0x1d 2362#define UVD_SYS_INT_EN__AVM_INT_EN__SHIFT 0x1f 2363#define UVD_SYS_INT_EN__PIF_ADDR_ERR_EN_MASK 0x00000001L 2364#define UVD_SYS_INT_EN__SEMA_WAIT_FAULT_TIMEOUT_EN_MASK 0x00000002L 2365#define UVD_SYS_INT_EN__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_EN_MASK 0x00000004L 2366#define UVD_SYS_INT_EN__CXW_WR_EN_MASK 0x00000008L 2367#define UVD_SYS_INT_EN__RBC_REG_PRIV_FAULT_EN_MASK 0x00000040L 2368#define UVD_SYS_INT_EN__LBSI_EN_MASK 0x00000800L 2369#define UVD_SYS_INT_EN__UDEC_EN_MASK 0x00001000L 2370#define UVD_SYS_INT_EN__JOB_DONE_EN_MASK 0x00010000L 2371#define UVD_SYS_INT_EN__SEMA_WAIT_FAIL_SIG_EN_MASK 0x00800000L 2372#define UVD_SYS_INT_EN__IDCT_EN_MASK 0x01000000L 2373#define UVD_SYS_INT_EN__MPRD_EN_MASK 0x02000000L 2374#define UVD_SYS_INT_EN__CLK_SWT_EN_MASK 0x08000000L 2375#define UVD_SYS_INT_EN__MIF_HWINT_EN_MASK 0x10000000L 2376#define UVD_SYS_INT_EN__MPRD_ERR_EN_MASK 0x20000000L 2377#define UVD_SYS_INT_EN__AVM_INT_EN_MASK 0x80000000L 2378//UVD_SYS_INT_STATUS 2379#define UVD_SYS_INT_STATUS__PIF_ADDR_ERR_INT__SHIFT 0x0 2380#define UVD_SYS_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT__SHIFT 0x1 2381#define UVD_SYS_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT__SHIFT 0x2 2382#define UVD_SYS_INT_STATUS__CXW_WR_INT__SHIFT 0x3 2383#define UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_INT__SHIFT 0x6 2384#define UVD_SYS_INT_STATUS__LBSI_INT__SHIFT 0xb 2385#define UVD_SYS_INT_STATUS__UDEC_INT__SHIFT 0xc 2386#define UVD_SYS_INT_STATUS__JOB_DONE_INT__SHIFT 0x10 2387#define UVD_SYS_INT_STATUS__GPCOM_INT__SHIFT 0x12 2388#define UVD_SYS_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT__SHIFT 0x17 2389#define UVD_SYS_INT_STATUS__IDCT_INT__SHIFT 0x18 2390#define UVD_SYS_INT_STATUS__MPRD_INT__SHIFT 0x19 2391#define UVD_SYS_INT_STATUS__CLK_SWT_INT__SHIFT 0x1b 2392#define UVD_SYS_INT_STATUS__MIF_HWINT__SHIFT 0x1c 2393#define UVD_SYS_INT_STATUS__MPRD_ERR_INT__SHIFT 0x1d 2394#define UVD_SYS_INT_STATUS__AVM_INT__SHIFT 0x1f 2395#define UVD_SYS_INT_STATUS__PIF_ADDR_ERR_INT_MASK 0x00000001L 2396#define UVD_SYS_INT_STATUS__SEMA_WAIT_FAULT_TIMEOUT_INT_MASK 0x00000002L 2397#define UVD_SYS_INT_STATUS__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_INT_MASK 0x00000004L 2398#define UVD_SYS_INT_STATUS__CXW_WR_INT_MASK 0x00000008L 2399#define UVD_SYS_INT_STATUS__RBC_REG_PRIV_FAULT_INT_MASK 0x00000040L 2400#define UVD_SYS_INT_STATUS__LBSI_INT_MASK 0x00000800L 2401#define UVD_SYS_INT_STATUS__UDEC_INT_MASK 0x00001000L 2402#define UVD_SYS_INT_STATUS__JOB_DONE_INT_MASK 0x00010000L 2403#define UVD_SYS_INT_STATUS__GPCOM_INT_MASK 0x00040000L 2404#define UVD_SYS_INT_STATUS__SEMA_WAIT_FAIL_SIG_INT_MASK 0x00800000L 2405#define UVD_SYS_INT_STATUS__IDCT_INT_MASK 0x01000000L 2406#define UVD_SYS_INT_STATUS__MPRD_INT_MASK 0x02000000L 2407#define UVD_SYS_INT_STATUS__CLK_SWT_INT_MASK 0x08000000L 2408#define UVD_SYS_INT_STATUS__MIF_HWINT_MASK 0x10000000L 2409#define UVD_SYS_INT_STATUS__MPRD_ERR_INT_MASK 0x20000000L 2410#define UVD_SYS_INT_STATUS__AVM_INT_MASK 0x80000000L 2411//UVD_SYS_INT_ACK 2412#define UVD_SYS_INT_ACK__PIF_ADDR_ERR_ACK__SHIFT 0x0 2413#define UVD_SYS_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK__SHIFT 0x1 2414#define UVD_SYS_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK__SHIFT 0x2 2415#define UVD_SYS_INT_ACK__CXW_WR_ACK__SHIFT 0x3 2416#define UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_ACK__SHIFT 0x6 2417#define UVD_SYS_INT_ACK__LBSI_ACK__SHIFT 0xb 2418#define UVD_SYS_INT_ACK__UDEC_ACK__SHIFT 0xc 2419#define UVD_SYS_INT_ACK__JOB_DONE_ACK__SHIFT 0x10 2420#define UVD_SYS_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK__SHIFT 0x17 2421#define UVD_SYS_INT_ACK__IDCT_ACK__SHIFT 0x18 2422#define UVD_SYS_INT_ACK__MPRD_ACK__SHIFT 0x19 2423#define UVD_SYS_INT_ACK__CLK_SWT_ACK__SHIFT 0x1b 2424#define UVD_SYS_INT_ACK__MIF_HWINT_ACK__SHIFT 0x1c 2425#define UVD_SYS_INT_ACK__MPRD_ERR_ACK__SHIFT 0x1d 2426#define UVD_SYS_INT_ACK__AVM_INT_ACK__SHIFT 0x1f 2427#define UVD_SYS_INT_ACK__PIF_ADDR_ERR_ACK_MASK 0x00000001L 2428#define UVD_SYS_INT_ACK__SEMA_WAIT_FAULT_TIMEOUT_ACK_MASK 0x00000002L 2429#define UVD_SYS_INT_ACK__SEMA_SIGNAL_INCOMPLETE_TIMEOUT_ACK_MASK 0x00000004L 2430#define UVD_SYS_INT_ACK__CXW_WR_ACK_MASK 0x00000008L 2431#define UVD_SYS_INT_ACK__RBC_REG_PRIV_FAULT_ACK_MASK 0x00000040L 2432#define UVD_SYS_INT_ACK__LBSI_ACK_MASK 0x00000800L 2433#define UVD_SYS_INT_ACK__UDEC_ACK_MASK 0x00001000L 2434#define UVD_SYS_INT_ACK__JOB_DONE_ACK_MASK 0x00010000L 2435#define UVD_SYS_INT_ACK__SEMA_WAIT_FAIL_SIG_ACK_MASK 0x00800000L 2436#define UVD_SYS_INT_ACK__IDCT_ACK_MASK 0x01000000L 2437#define UVD_SYS_INT_ACK__MPRD_ACK_MASK 0x02000000L 2438#define UVD_SYS_INT_ACK__CLK_SWT_ACK_MASK 0x08000000L 2439#define UVD_SYS_INT_ACK__MIF_HWINT_ACK_MASK 0x10000000L 2440#define UVD_SYS_INT_ACK__MPRD_ERR_ACK_MASK 0x20000000L 2441#define UVD_SYS_INT_ACK__AVM_INT_ACK_MASK 0x80000000L 2442//UVD_JOB_DONE 2443#define UVD_JOB_DONE__JOB_DONE__SHIFT 0x0 2444#define UVD_JOB_DONE__JOB_DONE_MASK 0x00000003L 2445//UVD_CBUF_ID 2446#define UVD_CBUF_ID__CBUF_ID__SHIFT 0x0 2447#define UVD_CBUF_ID__CBUF_ID_MASK 0xFFFFFFFFL 2448//UVD_CONTEXT_ID 2449#define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT 0x0 2450#define UVD_CONTEXT_ID__CONTEXT_ID_MASK 0xFFFFFFFFL 2451//UVD_CONTEXT_ID2 2452#define UVD_CONTEXT_ID2__CONTEXT_ID2__SHIFT 0x0 2453#define UVD_CONTEXT_ID2__CONTEXT_ID2_MASK 0xFFFFFFFFL 2454//UVD_NO_OP 2455#define UVD_NO_OP__NO_OP__SHIFT 0x0 2456#define UVD_NO_OP__NO_OP_MASK 0xFFFFFFFFL 2457//UVD_RB_BASE_LO 2458#define UVD_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 2459#define UVD_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L 2460//UVD_RB_BASE_HI 2461#define UVD_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 2462#define UVD_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL 2463//UVD_RB_SIZE 2464#define UVD_RB_SIZE__RB_SIZE__SHIFT 0x4 2465#define UVD_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L 2466//UVD_RB_RPTR 2467#define UVD_RB_RPTR__RB_RPTR__SHIFT 0x4 2468#define UVD_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 2469//UVD_RB_WPTR 2470#define UVD_RB_WPTR__RB_WPTR__SHIFT 0x4 2471#define UVD_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 2472//UVD_RB_BASE_LO2 2473#define UVD_RB_BASE_LO2__RB_BASE_LO__SHIFT 0x6 2474#define UVD_RB_BASE_LO2__RB_BASE_LO_MASK 0xFFFFFFC0L 2475//UVD_RB_BASE_HI2 2476#define UVD_RB_BASE_HI2__RB_BASE_HI__SHIFT 0x0 2477#define UVD_RB_BASE_HI2__RB_BASE_HI_MASK 0xFFFFFFFFL 2478//UVD_RB_SIZE2 2479#define UVD_RB_SIZE2__RB_SIZE__SHIFT 0x4 2480#define UVD_RB_SIZE2__RB_SIZE_MASK 0x007FFFF0L 2481//UVD_RB_RPTR2 2482#define UVD_RB_RPTR2__RB_RPTR__SHIFT 0x4 2483#define UVD_RB_RPTR2__RB_RPTR_MASK 0x007FFFF0L 2484//UVD_RB_WPTR2 2485#define UVD_RB_WPTR2__RB_WPTR__SHIFT 0x4 2486#define UVD_RB_WPTR2__RB_WPTR_MASK 0x007FFFF0L 2487//UVD_RB_BASE_LO3 2488#define UVD_RB_BASE_LO3__RB_BASE_LO__SHIFT 0x6 2489#define UVD_RB_BASE_LO3__RB_BASE_LO_MASK 0xFFFFFFC0L 2490//UVD_RB_BASE_HI3 2491#define UVD_RB_BASE_HI3__RB_BASE_HI__SHIFT 0x0 2492#define UVD_RB_BASE_HI3__RB_BASE_HI_MASK 0xFFFFFFFFL 2493//UVD_RB_SIZE3 2494#define UVD_RB_SIZE3__RB_SIZE__SHIFT 0x4 2495#define UVD_RB_SIZE3__RB_SIZE_MASK 0x007FFFF0L 2496//UVD_RB_RPTR3 2497#define UVD_RB_RPTR3__RB_RPTR__SHIFT 0x4 2498#define UVD_RB_RPTR3__RB_RPTR_MASK 0x007FFFF0L 2499//UVD_RB_WPTR3 2500#define UVD_RB_WPTR3__RB_WPTR__SHIFT 0x4 2501#define UVD_RB_WPTR3__RB_WPTR_MASK 0x007FFFF0L 2502//UVD_RB_BASE_LO4 2503#define UVD_RB_BASE_LO4__RB_BASE_LO__SHIFT 0x6 2504#define UVD_RB_BASE_LO4__RB_BASE_LO_MASK 0xFFFFFFC0L 2505//UVD_RB_BASE_HI4 2506#define UVD_RB_BASE_HI4__RB_BASE_HI__SHIFT 0x0 2507#define UVD_RB_BASE_HI4__RB_BASE_HI_MASK 0xFFFFFFFFL 2508//UVD_RB_SIZE4 2509#define UVD_RB_SIZE4__RB_SIZE__SHIFT 0x4 2510#define UVD_RB_SIZE4__RB_SIZE_MASK 0x007FFFF0L 2511//UVD_RB_RPTR4 2512#define UVD_RB_RPTR4__RB_RPTR__SHIFT 0x4 2513#define UVD_RB_RPTR4__RB_RPTR_MASK 0x007FFFF0L 2514//UVD_RB_WPTR4 2515#define UVD_RB_WPTR4__RB_WPTR__SHIFT 0x4 2516#define UVD_RB_WPTR4__RB_WPTR_MASK 0x007FFFF0L 2517//UVD_OUT_RB_BASE_LO 2518#define UVD_OUT_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 2519#define UVD_OUT_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L 2520//UVD_OUT_RB_BASE_HI 2521#define UVD_OUT_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 2522#define UVD_OUT_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL 2523//UVD_OUT_RB_SIZE 2524#define UVD_OUT_RB_SIZE__RB_SIZE__SHIFT 0x4 2525#define UVD_OUT_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L 2526//UVD_OUT_RB_RPTR 2527#define UVD_OUT_RB_RPTR__RB_RPTR__SHIFT 0x4 2528#define UVD_OUT_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 2529//UVD_OUT_RB_WPTR 2530#define UVD_OUT_RB_WPTR__RB_WPTR__SHIFT 0x4 2531#define UVD_OUT_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 2532//UVD_RB_ARB_CTRL 2533#define UVD_RB_ARB_CTRL__SRBM_DROP__SHIFT 0x0 2534#define UVD_RB_ARB_CTRL__SRBM_DIS__SHIFT 0x1 2535#define UVD_RB_ARB_CTRL__VCPU_DROP__SHIFT 0x2 2536#define UVD_RB_ARB_CTRL__VCPU_DIS__SHIFT 0x3 2537#define UVD_RB_ARB_CTRL__RBC_DROP__SHIFT 0x4 2538#define UVD_RB_ARB_CTRL__RBC_DIS__SHIFT 0x5 2539#define UVD_RB_ARB_CTRL__FWOFLD_DROP__SHIFT 0x6 2540#define UVD_RB_ARB_CTRL__FWOFLD_DIS__SHIFT 0x7 2541#define UVD_RB_ARB_CTRL__FAST_PATH_EN__SHIFT 0x8 2542#define UVD_RB_ARB_CTRL__SRBM_DROP_MASK 0x00000001L 2543#define UVD_RB_ARB_CTRL__SRBM_DIS_MASK 0x00000002L 2544#define UVD_RB_ARB_CTRL__VCPU_DROP_MASK 0x00000004L 2545#define UVD_RB_ARB_CTRL__VCPU_DIS_MASK 0x00000008L 2546#define UVD_RB_ARB_CTRL__RBC_DROP_MASK 0x00000010L 2547#define UVD_RB_ARB_CTRL__RBC_DIS_MASK 0x00000020L 2548#define UVD_RB_ARB_CTRL__FWOFLD_DROP_MASK 0x00000040L 2549#define UVD_RB_ARB_CTRL__FWOFLD_DIS_MASK 0x00000080L 2550#define UVD_RB_ARB_CTRL__FAST_PATH_EN_MASK 0x00000100L 2551//UVD_CTX_INDEX 2552#define UVD_CTX_INDEX__INDEX__SHIFT 0x0 2553#define UVD_CTX_INDEX__INDEX_MASK 0x000001FFL 2554//UVD_CTX_DATA 2555#define UVD_CTX_DATA__DATA__SHIFT 0x0 2556#define UVD_CTX_DATA__DATA_MASK 0xFFFFFFFFL 2557//UVD_CXW_WR 2558#define UVD_CXW_WR__DAT__SHIFT 0x0 2559#define UVD_CXW_WR__STAT__SHIFT 0x1f 2560#define UVD_CXW_WR__DAT_MASK 0x0FFFFFFFL 2561#define UVD_CXW_WR__STAT_MASK 0x80000000L 2562//UVD_CXW_WR_INT_ID 2563#define UVD_CXW_WR_INT_ID__ID__SHIFT 0x0 2564#define UVD_CXW_WR_INT_ID__ID_MASK 0x000000FFL 2565//UVD_CXW_WR_INT_CTX_ID 2566#define UVD_CXW_WR_INT_CTX_ID__ID__SHIFT 0x0 2567#define UVD_CXW_WR_INT_CTX_ID__ID_MASK 0x0FFFFFFFL 2568//UVD_CXW_INT_ID 2569#define UVD_CXW_INT_ID__ID__SHIFT 0x0 2570#define UVD_CXW_INT_ID__ID_MASK 0x000000FFL 2571//UVD_TOP_CTRL 2572#define UVD_TOP_CTRL__STANDARD__SHIFT 0x0 2573#define UVD_TOP_CTRL__STD_VERSION__SHIFT 0x4 2574#define UVD_TOP_CTRL__STANDARD_MASK 0x0000000FL 2575#define UVD_TOP_CTRL__STD_VERSION_MASK 0x000000F0L 2576//UVD_YBASE 2577#define UVD_YBASE__DUM__SHIFT 0x0 2578#define UVD_YBASE__DUM_MASK 0xFFFFFFFFL 2579//UVD_UVBASE 2580#define UVD_UVBASE__DUM__SHIFT 0x0 2581#define UVD_UVBASE__DUM_MASK 0xFFFFFFFFL 2582//UVD_PITCH 2583#define UVD_PITCH__DUM__SHIFT 0x0 2584#define UVD_PITCH__DUM_MASK 0xFFFFFFFFL 2585//UVD_WIDTH 2586#define UVD_WIDTH__DUM__SHIFT 0x0 2587#define UVD_WIDTH__DUM_MASK 0xFFFFFFFFL 2588//UVD_HEIGHT 2589#define UVD_HEIGHT__DUM__SHIFT 0x0 2590#define UVD_HEIGHT__DUM_MASK 0xFFFFFFFFL 2591//UVD_PICCOUNT 2592#define UVD_PICCOUNT__DUM__SHIFT 0x0 2593#define UVD_PICCOUNT__DUM_MASK 0xFFFFFFFFL 2594//UVD_SCRATCH_NP 2595#define UVD_SCRATCH_NP__DATA__SHIFT 0x0 2596#define UVD_SCRATCH_NP__DATA_MASK 0xFFFFFFFFL 2597//UVD_VERSION 2598#define UVD_VERSION__MINOR_VERSION__SHIFT 0x0 2599#define UVD_VERSION__MAJOR_VERSION__SHIFT 0x10 2600#define UVD_VERSION__MINOR_VERSION_MASK 0x0000FFFFL 2601#define UVD_VERSION__MAJOR_VERSION_MASK 0x0FFF0000L 2602//UVD_GP_SCRATCH0 2603#define UVD_GP_SCRATCH0__DATA__SHIFT 0x0 2604#define UVD_GP_SCRATCH0__DATA_MASK 0xFFFFFFFFL 2605//UVD_GP_SCRATCH1 2606#define UVD_GP_SCRATCH1__DATA__SHIFT 0x0 2607#define UVD_GP_SCRATCH1__DATA_MASK 0xFFFFFFFFL 2608//UVD_GP_SCRATCH2 2609#define UVD_GP_SCRATCH2__DATA__SHIFT 0x0 2610#define UVD_GP_SCRATCH2__DATA_MASK 0xFFFFFFFFL 2611//UVD_GP_SCRATCH3 2612#define UVD_GP_SCRATCH3__DATA__SHIFT 0x0 2613#define UVD_GP_SCRATCH3__DATA_MASK 0xFFFFFFFFL 2614//UVD_GP_SCRATCH4 2615#define UVD_GP_SCRATCH4__DATA__SHIFT 0x0 2616#define UVD_GP_SCRATCH4__DATA_MASK 0xFFFFFFFFL 2617//UVD_GP_SCRATCH5 2618#define UVD_GP_SCRATCH5__DATA__SHIFT 0x0 2619#define UVD_GP_SCRATCH5__DATA_MASK 0xFFFFFFFFL 2620//UVD_GP_SCRATCH6 2621#define UVD_GP_SCRATCH6__DATA__SHIFT 0x0 2622#define UVD_GP_SCRATCH6__DATA_MASK 0xFFFFFFFFL 2623//UVD_GP_SCRATCH7 2624#define UVD_GP_SCRATCH7__DATA__SHIFT 0x0 2625#define UVD_GP_SCRATCH7__DATA_MASK 0xFFFFFFFFL 2626//UVD_GP_SCRATCH8 2627#define UVD_GP_SCRATCH8__DATA__SHIFT 0x0 2628#define UVD_GP_SCRATCH8__DATA_MASK 0xFFFFFFFFL 2629//UVD_GP_SCRATCH9 2630#define UVD_GP_SCRATCH9__DATA__SHIFT 0x0 2631#define UVD_GP_SCRATCH9__DATA_MASK 0xFFFFFFFFL 2632//UVD_GP_SCRATCH10 2633#define UVD_GP_SCRATCH10__DATA__SHIFT 0x0 2634#define UVD_GP_SCRATCH10__DATA_MASK 0xFFFFFFFFL 2635//UVD_GP_SCRATCH11 2636#define UVD_GP_SCRATCH11__DATA__SHIFT 0x0 2637#define UVD_GP_SCRATCH11__DATA_MASK 0xFFFFFFFFL 2638//UVD_GP_SCRATCH12 2639#define UVD_GP_SCRATCH12__DATA__SHIFT 0x0 2640#define UVD_GP_SCRATCH12__DATA_MASK 0xFFFFFFFFL 2641//UVD_GP_SCRATCH13 2642#define UVD_GP_SCRATCH13__DATA__SHIFT 0x0 2643#define UVD_GP_SCRATCH13__DATA_MASK 0xFFFFFFFFL 2644//UVD_GP_SCRATCH14 2645#define UVD_GP_SCRATCH14__DATA__SHIFT 0x0 2646#define UVD_GP_SCRATCH14__DATA_MASK 0xFFFFFFFFL 2647//UVD_GP_SCRATCH15 2648#define UVD_GP_SCRATCH15__DATA__SHIFT 0x0 2649#define UVD_GP_SCRATCH15__DATA_MASK 0xFFFFFFFFL 2650//UVD_GP_SCRATCH16 2651#define UVD_GP_SCRATCH16__DATA__SHIFT 0x0 2652#define UVD_GP_SCRATCH16__DATA_MASK 0xFFFFFFFFL 2653//UVD_GP_SCRATCH17 2654#define UVD_GP_SCRATCH17__DATA__SHIFT 0x0 2655#define UVD_GP_SCRATCH17__DATA_MASK 0xFFFFFFFFL 2656//UVD_GP_SCRATCH18 2657#define UVD_GP_SCRATCH18__DATA__SHIFT 0x0 2658#define UVD_GP_SCRATCH18__DATA_MASK 0xFFFFFFFFL 2659//UVD_GP_SCRATCH19 2660#define UVD_GP_SCRATCH19__DATA__SHIFT 0x0 2661#define UVD_GP_SCRATCH19__DATA_MASK 0xFFFFFFFFL 2662//UVD_GP_SCRATCH20 2663#define UVD_GP_SCRATCH20__DATA__SHIFT 0x0 2664#define UVD_GP_SCRATCH20__DATA_MASK 0xFFFFFFFFL 2665//UVD_GP_SCRATCH21 2666#define UVD_GP_SCRATCH21__DATA__SHIFT 0x0 2667#define UVD_GP_SCRATCH21__DATA_MASK 0xFFFFFFFFL 2668//UVD_GP_SCRATCH22 2669#define UVD_GP_SCRATCH22__DATA__SHIFT 0x0 2670#define UVD_GP_SCRATCH22__DATA_MASK 0xFFFFFFFFL 2671//UVD_GP_SCRATCH23 2672#define UVD_GP_SCRATCH23__DATA__SHIFT 0x0 2673#define UVD_GP_SCRATCH23__DATA_MASK 0xFFFFFFFFL 2674 2675 2676// addressBlock: uvd0_ecpudec 2677//UVD_VCPU_CACHE_OFFSET0 2678#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 2679#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x001FFFFFL 2680//UVD_VCPU_CACHE_SIZE0 2681#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x0 2682#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x001FFFFFL 2683//UVD_VCPU_CACHE_OFFSET1 2684#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0 2685#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x001FFFFFL 2686//UVD_VCPU_CACHE_SIZE1 2687#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT 0x0 2688#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x001FFFFFL 2689//UVD_VCPU_CACHE_OFFSET2 2690#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0 2691#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK 0x001FFFFFL 2692//UVD_VCPU_CACHE_SIZE2 2693#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x0 2694#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x001FFFFFL 2695//UVD_VCPU_CACHE_OFFSET3 2696#define UVD_VCPU_CACHE_OFFSET3__CACHE_OFFSET3__SHIFT 0x0 2697#define UVD_VCPU_CACHE_OFFSET3__CACHE_OFFSET3_MASK 0x001FFFFFL 2698//UVD_VCPU_CACHE_SIZE3 2699#define UVD_VCPU_CACHE_SIZE3__CACHE_SIZE3__SHIFT 0x0 2700#define UVD_VCPU_CACHE_SIZE3__CACHE_SIZE3_MASK 0x001FFFFFL 2701//UVD_VCPU_CACHE_OFFSET4 2702#define UVD_VCPU_CACHE_OFFSET4__CACHE_OFFSET4__SHIFT 0x0 2703#define UVD_VCPU_CACHE_OFFSET4__CACHE_OFFSET4_MASK 0x001FFFFFL 2704//UVD_VCPU_CACHE_SIZE4 2705#define UVD_VCPU_CACHE_SIZE4__CACHE_SIZE4__SHIFT 0x0 2706#define UVD_VCPU_CACHE_SIZE4__CACHE_SIZE4_MASK 0x001FFFFFL 2707//UVD_VCPU_CACHE_OFFSET5 2708#define UVD_VCPU_CACHE_OFFSET5__CACHE_OFFSET5__SHIFT 0x0 2709#define UVD_VCPU_CACHE_OFFSET5__CACHE_OFFSET5_MASK 0x001FFFFFL 2710//UVD_VCPU_CACHE_SIZE5 2711#define UVD_VCPU_CACHE_SIZE5__CACHE_SIZE5__SHIFT 0x0 2712#define UVD_VCPU_CACHE_SIZE5__CACHE_SIZE5_MASK 0x001FFFFFL 2713//UVD_VCPU_CACHE_OFFSET6 2714#define UVD_VCPU_CACHE_OFFSET6__CACHE_OFFSET6__SHIFT 0x0 2715#define UVD_VCPU_CACHE_OFFSET6__CACHE_OFFSET6_MASK 0x001FFFFFL 2716//UVD_VCPU_CACHE_SIZE6 2717#define UVD_VCPU_CACHE_SIZE6__CACHE_SIZE6__SHIFT 0x0 2718#define UVD_VCPU_CACHE_SIZE6__CACHE_SIZE6_MASK 0x001FFFFFL 2719//UVD_VCPU_CACHE_OFFSET7 2720#define UVD_VCPU_CACHE_OFFSET7__CACHE_OFFSET7__SHIFT 0x0 2721#define UVD_VCPU_CACHE_OFFSET7__CACHE_OFFSET7_MASK 0x001FFFFFL 2722//UVD_VCPU_CACHE_SIZE7 2723#define UVD_VCPU_CACHE_SIZE7__CACHE_SIZE7__SHIFT 0x0 2724#define UVD_VCPU_CACHE_SIZE7__CACHE_SIZE7_MASK 0x001FFFFFL 2725//UVD_VCPU_CACHE_OFFSET8 2726#define UVD_VCPU_CACHE_OFFSET8__CACHE_OFFSET8__SHIFT 0x0 2727#define UVD_VCPU_CACHE_OFFSET8__CACHE_OFFSET8_MASK 0x001FFFFFL 2728//UVD_VCPU_CACHE_SIZE8 2729#define UVD_VCPU_CACHE_SIZE8__CACHE_SIZE8__SHIFT 0x0 2730#define UVD_VCPU_CACHE_SIZE8__CACHE_SIZE8_MASK 0x001FFFFFL 2731//UVD_VCPU_NONCACHE_OFFSET0 2732#define UVD_VCPU_NONCACHE_OFFSET0__NONCACHE_OFFSET0__SHIFT 0x0 2733#define UVD_VCPU_NONCACHE_OFFSET0__NONCACHE_OFFSET0_MASK 0x01FFFFFFL 2734//UVD_VCPU_NONCACHE_SIZE0 2735#define UVD_VCPU_NONCACHE_SIZE0__NONCACHE_SIZE0__SHIFT 0x0 2736#define UVD_VCPU_NONCACHE_SIZE0__NONCACHE_SIZE0_MASK 0x001FFFFFL 2737//UVD_VCPU_NONCACHE_OFFSET1 2738#define UVD_VCPU_NONCACHE_OFFSET1__NONCACHE_OFFSET1__SHIFT 0x0 2739#define UVD_VCPU_NONCACHE_OFFSET1__NONCACHE_OFFSET1_MASK 0x01FFFFFFL 2740//UVD_VCPU_NONCACHE_SIZE1 2741#define UVD_VCPU_NONCACHE_SIZE1__NONCACHE_SIZE1__SHIFT 0x0 2742#define UVD_VCPU_NONCACHE_SIZE1__NONCACHE_SIZE1_MASK 0x001FFFFFL 2743//UVD_VCPU_CNTL 2744#define UVD_VCPU_CNTL__IRQ_ERR__SHIFT 0x0 2745#define UVD_VCPU_CNTL__PMB_ED_ENABLE__SHIFT 0x5 2746#define UVD_VCPU_CNTL__PMB_SOFT_RESET__SHIFT 0x6 2747#define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x7 2748#define UVD_VCPU_CNTL__ABORT_REQ__SHIFT 0x8 2749#define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x9 2750#define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0xa 2751#define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0xb 2752#define UVD_VCPU_CNTL__JTAG_EN__SHIFT 0x10 2753#define UVD_VCPU_CNTL__TIMEOUT_DIS__SHIFT 0x12 2754#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 2755#define UVD_VCPU_CNTL__BLK_RST__SHIFT 0x1c 2756#define UVD_VCPU_CNTL__IRQ_ERR_MASK 0x0000000FL 2757#define UVD_VCPU_CNTL__PMB_ED_ENABLE_MASK 0x00000020L 2758#define UVD_VCPU_CNTL__PMB_SOFT_RESET_MASK 0x00000040L 2759#define UVD_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x00000080L 2760#define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x00000100L 2761#define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L 2762#define UVD_VCPU_CNTL__TRCE_EN_MASK 0x00000400L 2763#define UVD_VCPU_CNTL__TRCE_MUX_MASK 0x00001800L 2764#define UVD_VCPU_CNTL__JTAG_EN_MASK 0x00010000L 2765#define UVD_VCPU_CNTL__TIMEOUT_DIS_MASK 0x00040000L 2766#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK 0x0FF00000L 2767#define UVD_VCPU_CNTL__BLK_RST_MASK 0x10000000L 2768//UVD_VCPU_PRID 2769#define UVD_VCPU_PRID__PRID__SHIFT 0x0 2770#define UVD_VCPU_PRID__PRID_MASK 0x0000FFFFL 2771//UVD_VCPU_TRCE 2772#define UVD_VCPU_TRCE__PC__SHIFT 0x0 2773#define UVD_VCPU_TRCE__PC_MASK 0x0FFFFFFFL 2774//UVD_VCPU_TRCE_RD 2775#define UVD_VCPU_TRCE_RD__DATA__SHIFT 0x0 2776#define UVD_VCPU_TRCE_RD__DATA_MASK 0xFFFFFFFFL 2777 2778 2779// addressBlock: uvd0_uvd_mpcdec 2780//UVD_MP_SWAP_CNTL 2781#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP__SHIFT 0x0 2782#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT 0x2 2783#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP__SHIFT 0x4 2784#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP__SHIFT 0x6 2785#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP__SHIFT 0x8 2786#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT 0xa 2787#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP__SHIFT 0xc 2788#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP__SHIFT 0xe 2789#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP__SHIFT 0x10 2790#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP__SHIFT 0x12 2791#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT 0x14 2792#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP__SHIFT 0x16 2793#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP__SHIFT 0x18 2794#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP__SHIFT 0x1a 2795#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP__SHIFT 0x1c 2796#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP__SHIFT 0x1e 2797#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP_MASK 0x00000003L 2798#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP_MASK 0x0000000CL 2799#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP_MASK 0x00000030L 2800#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP_MASK 0x000000C0L 2801#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP_MASK 0x00000300L 2802#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP_MASK 0x00000C00L 2803#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP_MASK 0x00003000L 2804#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP_MASK 0x0000C000L 2805#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP_MASK 0x00030000L 2806#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP_MASK 0x000C0000L 2807#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP_MASK 0x00300000L 2808#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP_MASK 0x00C00000L 2809#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP_MASK 0x03000000L 2810#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP_MASK 0x0C000000L 2811#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP_MASK 0x30000000L 2812#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP_MASK 0xC0000000L 2813//UVD_MPC_LUMA_SRCH 2814#define UVD_MPC_LUMA_SRCH__CNTR__SHIFT 0x0 2815#define UVD_MPC_LUMA_SRCH__CNTR_MASK 0xFFFFFFFFL 2816//UVD_MPC_LUMA_HIT 2817#define UVD_MPC_LUMA_HIT__CNTR__SHIFT 0x0 2818#define UVD_MPC_LUMA_HIT__CNTR_MASK 0xFFFFFFFFL 2819//UVD_MPC_LUMA_HITPEND 2820#define UVD_MPC_LUMA_HITPEND__CNTR__SHIFT 0x0 2821#define UVD_MPC_LUMA_HITPEND__CNTR_MASK 0xFFFFFFFFL 2822//UVD_MPC_CHROMA_SRCH 2823#define UVD_MPC_CHROMA_SRCH__CNTR__SHIFT 0x0 2824#define UVD_MPC_CHROMA_SRCH__CNTR_MASK 0xFFFFFFFFL 2825//UVD_MPC_CHROMA_HIT 2826#define UVD_MPC_CHROMA_HIT__CNTR__SHIFT 0x0 2827#define UVD_MPC_CHROMA_HIT__CNTR_MASK 0xFFFFFFFFL 2828//UVD_MPC_CHROMA_HITPEND 2829#define UVD_MPC_CHROMA_HITPEND__CNTR__SHIFT 0x0 2830#define UVD_MPC_CHROMA_HITPEND__CNTR_MASK 0xFFFFFFFFL 2831//UVD_MPC_CNTL 2832#define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3 2833#define UVD_MPC_CNTL__PERF_RST__SHIFT 0x6 2834#define UVD_MPC_CNTL__AVE_WEIGHT__SHIFT 0x10 2835#define UVD_MPC_CNTL__URGENT_EN__SHIFT 0x12 2836#define UVD_MPC_CNTL__SMPAT_REQ_SPEED_UP__SHIFT 0x13 2837#define UVD_MPC_CNTL__TEST_MODE_EN__SHIFT 0x14 2838#define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x00000038L 2839#define UVD_MPC_CNTL__PERF_RST_MASK 0x00000040L 2840#define UVD_MPC_CNTL__AVE_WEIGHT_MASK 0x00030000L 2841#define UVD_MPC_CNTL__URGENT_EN_MASK 0x00040000L 2842#define UVD_MPC_CNTL__SMPAT_REQ_SPEED_UP_MASK 0x00080000L 2843#define UVD_MPC_CNTL__TEST_MODE_EN_MASK 0x00100000L 2844//UVD_MPC_PITCH 2845#define UVD_MPC_PITCH__LUMA_PITCH__SHIFT 0x0 2846#define UVD_MPC_PITCH__LUMA_PITCH_MASK 0x000007FFL 2847//UVD_MPC_SET_MUXA0 2848#define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0 2849#define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 2850#define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc 2851#define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 2852#define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18 2853#define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x0000003FL 2854#define UVD_MPC_SET_MUXA0__VARA_1_MASK 0x00000FC0L 2855#define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x0003F000L 2856#define UVD_MPC_SET_MUXA0__VARA_3_MASK 0x00FC0000L 2857#define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3F000000L 2858//UVD_MPC_SET_MUXA1 2859#define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0 2860#define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x6 2861#define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc 2862#define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x0000003FL 2863#define UVD_MPC_SET_MUXA1__VARA_6_MASK 0x00000FC0L 2864#define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x0003F000L 2865//UVD_MPC_SET_MUXB0 2866#define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0 2867#define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6 2868#define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc 2869#define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12 2870#define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18 2871#define UVD_MPC_SET_MUXB0__VARB_0_MASK 0x0000003FL 2872#define UVD_MPC_SET_MUXB0__VARB_1_MASK 0x00000FC0L 2873#define UVD_MPC_SET_MUXB0__VARB_2_MASK 0x0003F000L 2874#define UVD_MPC_SET_MUXB0__VARB_3_MASK 0x00FC0000L 2875#define UVD_MPC_SET_MUXB0__VARB_4_MASK 0x3F000000L 2876//UVD_MPC_SET_MUXB1 2877#define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x0 2878#define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6 2879#define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0xc 2880#define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x0000003FL 2881#define UVD_MPC_SET_MUXB1__VARB_6_MASK 0x00000FC0L 2882#define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x0003F000L 2883//UVD_MPC_SET_MUX 2884#define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0 2885#define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3 2886#define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 2887#define UVD_MPC_SET_MUX__SET_0_MASK 0x00000007L 2888#define UVD_MPC_SET_MUX__SET_1_MASK 0x00000038L 2889#define UVD_MPC_SET_MUX__SET_2_MASK 0x000001C0L 2890//UVD_MPC_SET_ALU 2891#define UVD_MPC_SET_ALU__FUNCT__SHIFT 0x0 2892#define UVD_MPC_SET_ALU__OPERAND__SHIFT 0x4 2893#define UVD_MPC_SET_ALU__FUNCT_MASK 0x00000007L 2894#define UVD_MPC_SET_ALU__OPERAND_MASK 0x00000FF0L 2895//UVD_MPC_PERF0 2896#define UVD_MPC_PERF0__MAX_LAT__SHIFT 0x0 2897#define UVD_MPC_PERF0__MAX_LAT_MASK 0x000003FFL 2898//UVD_MPC_PERF1 2899#define UVD_MPC_PERF1__AVE_LAT__SHIFT 0x0 2900#define UVD_MPC_PERF1__AVE_LAT_MASK 0x000003FFL 2901 2902 2903// addressBlock: uvd0_uvd_rbcdec 2904//UVD_RBC_IB_SIZE 2905#define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT 0x4 2906#define UVD_RBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L 2907//UVD_RBC_IB_SIZE_UPDATE 2908#define UVD_RBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE__SHIFT 0x4 2909#define UVD_RBC_IB_SIZE_UPDATE__REMAIN_IB_SIZE_MASK 0x007FFFF0L 2910//UVD_RBC_RB_CNTL 2911#define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x0 2912#define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x8 2913#define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x10 2914#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14 2915#define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x18 2916#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1c 2917#define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK 0x0000001FL 2918#define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK 0x00001F00L 2919#define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x00010000L 2920#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x00100000L 2921#define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x01000000L 2922#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000L 2923//UVD_RBC_RB_RPTR_ADDR 2924#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x0 2925#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFFL 2926//UVD_RBC_RB_RPTR 2927#define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT 0x4 2928#define UVD_RBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 2929//UVD_RBC_RB_WPTR 2930#define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT 0x4 2931#define UVD_RBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 2932//UVD_RBC_VCPU_ACCESS 2933#define UVD_RBC_VCPU_ACCESS__ENABLE_RBC__SHIFT 0x0 2934#define UVD_RBC_VCPU_ACCESS__ENABLE_RBC_MASK 0x00000001L 2935//UVD_RBC_READ_REQ_URGENT_CNTL 2936#define UVD_RBC_READ_REQ_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK__SHIFT 0x0 2937#define UVD_RBC_READ_REQ_URGENT_CNTL__CMD_READ_REQ_PRIORITY_MARK_MASK 0x00000003L 2938//UVD_RBC_RB_WPTR_CNTL 2939#define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x0 2940#define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER_MASK 0x00007FFFL 2941//UVD_RBC_WPTR_STATUS 2942#define UVD_RBC_WPTR_STATUS__RB_WPTR_IN_USE__SHIFT 0x4 2943#define UVD_RBC_WPTR_STATUS__RB_WPTR_IN_USE_MASK 0x007FFFF0L 2944//UVD_RBC_WPTR_POLL_CNTL 2945#define UVD_RBC_WPTR_POLL_CNTL__POLL_FREQ__SHIFT 0x0 2946#define UVD_RBC_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 2947#define UVD_RBC_WPTR_POLL_CNTL__POLL_FREQ_MASK 0x0000FFFFL 2948#define UVD_RBC_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 2949//UVD_RBC_WPTR_POLL_ADDR 2950#define UVD_RBC_WPTR_POLL_ADDR__POLL_ADDR__SHIFT 0x2 2951#define UVD_RBC_WPTR_POLL_ADDR__POLL_ADDR_MASK 0xFFFFFFFCL 2952//UVD_SEMA_CMD 2953#define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0 2954#define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4 2955#define UVD_SEMA_CMD__MODE__SHIFT 0x6 2956#define UVD_SEMA_CMD__VMID_EN__SHIFT 0x7 2957#define UVD_SEMA_CMD__VMID__SHIFT 0x8 2958#define UVD_SEMA_CMD__REQ_CMD_MASK 0x0000000FL 2959#define UVD_SEMA_CMD__WR_PHASE_MASK 0x00000030L 2960#define UVD_SEMA_CMD__MODE_MASK 0x00000040L 2961#define UVD_SEMA_CMD__VMID_EN_MASK 0x00000080L 2962#define UVD_SEMA_CMD__VMID_MASK 0x00000F00L 2963//UVD_SEMA_ADDR_LOW 2964#define UVD_SEMA_ADDR_LOW__ADDR_26_3__SHIFT 0x0 2965#define UVD_SEMA_ADDR_LOW__ADDR_26_3_MASK 0x00FFFFFFL 2966//UVD_SEMA_ADDR_HIGH 2967#define UVD_SEMA_ADDR_HIGH__ADDR_47_27__SHIFT 0x0 2968#define UVD_SEMA_ADDR_HIGH__ADDR_47_27_MASK 0x001FFFFFL 2969//UVD_ENGINE_CNTL 2970#define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x0 2971#define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1 2972#define UVD_ENGINE_CNTL__NJ_PF_HANDLE_DISABLE__SHIFT 0x2 2973#define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x00000001L 2974#define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x00000002L 2975#define UVD_ENGINE_CNTL__NJ_PF_HANDLE_DISABLE_MASK 0x00000004L 2976//UVD_SEMA_TIMEOUT_STATUS 2977#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x0 2978#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT 0x1 2979#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x2 2980#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT 0x3 2981#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000001L 2982#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x00000002L 2983#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000004L 2984#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK 0x00000008L 2985//UVD_SEMA_CNTL 2986#define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0 2987#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x1 2988#define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x00000001L 2989#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x00000002L 2990//UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 2991#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT 0x0 2992#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT 0x1 2993#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 2994#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK 0x00000001L 2995#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK 0x001FFFFEL 2996#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L 2997//UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 2998#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT 0x0 2999#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT 0x1 3000#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 3001#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK 0x00000001L 3002#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK 0x001FFFFEL 3003#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L 3004//UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 3005#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT 0x0 3006#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT 0x1 3007#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 3008#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK 0x00000001L 3009#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK 0x001FFFFEL 3010#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L 3011//UVD_JOB_START 3012#define UVD_JOB_START__JOB_START__SHIFT 0x0 3013#define UVD_JOB_START__JOB_START_MASK 0x00000001L 3014//UVD_RBC_BUF_STATUS 3015#define UVD_RBC_BUF_STATUS__RB_BUF_VALID__SHIFT 0x0 3016#define UVD_RBC_BUF_STATUS__IB_BUF_VALID__SHIFT 0x8 3017#define UVD_RBC_BUF_STATUS__RB_BUF_RD_ADDR__SHIFT 0x10 3018#define UVD_RBC_BUF_STATUS__IB_BUF_RD_ADDR__SHIFT 0x13 3019#define UVD_RBC_BUF_STATUS__RB_BUF_WR_ADDR__SHIFT 0x16 3020#define UVD_RBC_BUF_STATUS__IB_BUF_WR_ADDR__SHIFT 0x19 3021#define UVD_RBC_BUF_STATUS__RB_BUF_VALID_MASK 0x000000FFL 3022#define UVD_RBC_BUF_STATUS__IB_BUF_VALID_MASK 0x0000FF00L 3023#define UVD_RBC_BUF_STATUS__RB_BUF_RD_ADDR_MASK 0x00070000L 3024#define UVD_RBC_BUF_STATUS__IB_BUF_RD_ADDR_MASK 0x00380000L 3025#define UVD_RBC_BUF_STATUS__RB_BUF_WR_ADDR_MASK 0x01C00000L 3026#define UVD_RBC_BUF_STATUS__IB_BUF_WR_ADDR_MASK 0x0E000000L 3027 3028 3029// addressBlock: uvd0_uvdgendec 3030//UVD_LCM_CGC_CNTRL 3031#define UVD_LCM_CGC_CNTRL__FORCE_OFF__SHIFT 0x12 3032#define UVD_LCM_CGC_CNTRL__FORCE_ON__SHIFT 0x13 3033#define UVD_LCM_CGC_CNTRL__OFF_DELAY__SHIFT 0x14 3034#define UVD_LCM_CGC_CNTRL__ON_DELAY__SHIFT 0x1c 3035#define UVD_LCM_CGC_CNTRL__FORCE_OFF_MASK 0x00040000L 3036#define UVD_LCM_CGC_CNTRL__FORCE_ON_MASK 0x00080000L 3037#define UVD_LCM_CGC_CNTRL__OFF_DELAY_MASK 0x0FF00000L 3038#define UVD_LCM_CGC_CNTRL__ON_DELAY_MASK 0xF0000000L 3039 3040 3041// addressBlock: uvd0_lmi_adpdec 3042//UVD_LMI_RBC_RB_64BIT_BAR_LOW 3043#define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3044#define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3045//UVD_LMI_RBC_RB_64BIT_BAR_HIGH 3046#define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3047#define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3048//UVD_LMI_RBC_IB_64BIT_BAR_LOW 3049#define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3050#define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3051//UVD_LMI_RBC_IB_64BIT_BAR_HIGH 3052#define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3053#define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3054//UVD_LMI_LBSI_64BIT_BAR_LOW 3055#define UVD_LMI_LBSI_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3056#define UVD_LMI_LBSI_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3057//UVD_LMI_LBSI_64BIT_BAR_HIGH 3058#define UVD_LMI_LBSI_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3059#define UVD_LMI_LBSI_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3060//UVD_LMI_VCPU_NC0_64BIT_BAR_LOW 3061#define UVD_LMI_VCPU_NC0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3062#define UVD_LMI_VCPU_NC0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3063//UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH 3064#define UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3065#define UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3066//UVD_LMI_VCPU_NC1_64BIT_BAR_LOW 3067#define UVD_LMI_VCPU_NC1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3068#define UVD_LMI_VCPU_NC1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3069//UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH 3070#define UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3071#define UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3072//UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 3073#define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3074#define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3075//UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 3076#define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3077#define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3078//UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW 3079#define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3080#define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3081//UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH 3082#define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3083#define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3084//UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW 3085#define UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3086#define UVD_LMI_VCPU_CACHE8_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3087//UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH 3088#define UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3089#define UVD_LMI_VCPU_CACHE8_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3090//UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW 3091#define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3092#define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3093//UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH 3094#define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3095#define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3096//UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW 3097#define UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3098#define UVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3099//UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH 3100#define UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3101#define UVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3102//UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW 3103#define UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3104#define UVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3105//UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH 3106#define UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3107#define UVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3108//UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW 3109#define UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3110#define UVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3111//UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH 3112#define UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3113#define UVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3114//UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW 3115#define UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3116#define UVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3117//UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH 3118#define UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3119#define UVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3120//UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW 3121#define UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3122#define UVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3123//UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH 3124#define UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3125#define UVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3126//UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW 3127#define UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3128#define UVD_LMI_MMSCH_NC0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3129//UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH 3130#define UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3131#define UVD_LMI_MMSCH_NC0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3132//UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW 3133#define UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3134#define UVD_LMI_MMSCH_NC1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3135//UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH 3136#define UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3137#define UVD_LMI_MMSCH_NC1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3138//UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW 3139#define UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3140#define UVD_LMI_MMSCH_NC2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3141//UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH 3142#define UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3143#define UVD_LMI_MMSCH_NC2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3144//UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW 3145#define UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3146#define UVD_LMI_MMSCH_NC3_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3147//UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH 3148#define UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3149#define UVD_LMI_MMSCH_NC3_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3150//UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW 3151#define UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3152#define UVD_LMI_MMSCH_NC4_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3153//UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH 3154#define UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3155#define UVD_LMI_MMSCH_NC4_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3156//UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW 3157#define UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3158#define UVD_LMI_MMSCH_NC5_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3159//UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH 3160#define UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3161#define UVD_LMI_MMSCH_NC5_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3162//UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW 3163#define UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3164#define UVD_LMI_MMSCH_NC6_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3165//UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH 3166#define UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3167#define UVD_LMI_MMSCH_NC6_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3168//UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW 3169#define UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 3170#define UVD_LMI_MMSCH_NC7_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 3171//UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH 3172#define UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 3173#define UVD_LMI_MMSCH_NC7_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 3174//UVD_LMI_MMSCH_NC_VMID 3175#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC0_VMID__SHIFT 0x0 3176#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC1_VMID__SHIFT 0x4 3177#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC2_VMID__SHIFT 0x8 3178#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC3_VMID__SHIFT 0xc 3179#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC4_VMID__SHIFT 0x10 3180#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC5_VMID__SHIFT 0x14 3181#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC6_VMID__SHIFT 0x18 3182#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC7_VMID__SHIFT 0x1c 3183#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC0_VMID_MASK 0x0000000FL 3184#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC1_VMID_MASK 0x000000F0L 3185#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC2_VMID_MASK 0x00000F00L 3186#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC3_VMID_MASK 0x0000F000L 3187#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC4_VMID_MASK 0x000F0000L 3188#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC5_VMID_MASK 0x00F00000L 3189#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC6_VMID_MASK 0x0F000000L 3190#define UVD_LMI_MMSCH_NC_VMID__MMSCH_NC7_VMID_MASK 0xF0000000L 3191//UVD_LMI_MMSCH_CTRL 3192#define UVD_LMI_MMSCH_CTRL__MMSCH_DATA_COHERENCY_EN__SHIFT 0x0 3193#define UVD_LMI_MMSCH_CTRL__MMSCH_VM__SHIFT 0x1 3194#define UVD_LMI_MMSCH_CTRL__MMSCH_R_MC_SWAP__SHIFT 0x3 3195#define UVD_LMI_MMSCH_CTRL__MMSCH_W_MC_SWAP__SHIFT 0x5 3196#define UVD_LMI_MMSCH_CTRL__MMSCH_RD__SHIFT 0x7 3197#define UVD_LMI_MMSCH_CTRL__MMSCH_WR__SHIFT 0x9 3198#define UVD_LMI_MMSCH_CTRL__MMSCH_RD_DROP__SHIFT 0xb 3199#define UVD_LMI_MMSCH_CTRL__MMSCH_WR_DROP__SHIFT 0xc 3200#define UVD_LMI_MMSCH_CTRL__MMSCH_DATA_COHERENCY_EN_MASK 0x00000001L 3201#define UVD_LMI_MMSCH_CTRL__MMSCH_VM_MASK 0x00000002L 3202#define UVD_LMI_MMSCH_CTRL__MMSCH_R_MC_SWAP_MASK 0x00000018L 3203#define UVD_LMI_MMSCH_CTRL__MMSCH_W_MC_SWAP_MASK 0x00000060L 3204#define UVD_LMI_MMSCH_CTRL__MMSCH_RD_MASK 0x00000180L 3205#define UVD_LMI_MMSCH_CTRL__MMSCH_WR_MASK 0x00000600L 3206#define UVD_LMI_MMSCH_CTRL__MMSCH_RD_DROP_MASK 0x00000800L 3207#define UVD_LMI_MMSCH_CTRL__MMSCH_WR_DROP_MASK 0x00001000L 3208//UVD_LMI_ARB_CTRL2 3209#define UVD_LMI_ARB_CTRL2__CENC_RD_WAIT_EN__SHIFT 0x0 3210#define UVD_LMI_ARB_CTRL2__ATOMIC_WR_WAIT_EN__SHIFT 0x1 3211#define UVD_LMI_ARB_CTRL2__CENC_RD_MAX_BURST__SHIFT 0x2 3212#define UVD_LMI_ARB_CTRL2__ATOMIC_WR_MAX_BURST__SHIFT 0x6 3213#define UVD_LMI_ARB_CTRL2__MIF_RD_REQ_RET_MAX__SHIFT 0xa 3214#define UVD_LMI_ARB_CTRL2__MIF_WR_REQ_RET_MAX__SHIFT 0x14 3215#define UVD_LMI_ARB_CTRL2__CENC_RD_WAIT_EN_MASK 0x00000001L 3216#define UVD_LMI_ARB_CTRL2__ATOMIC_WR_WAIT_EN_MASK 0x00000002L 3217#define UVD_LMI_ARB_CTRL2__CENC_RD_MAX_BURST_MASK 0x0000003CL 3218#define UVD_LMI_ARB_CTRL2__ATOMIC_WR_MAX_BURST_MASK 0x000003C0L 3219#define UVD_LMI_ARB_CTRL2__MIF_RD_REQ_RET_MAX_MASK 0x000FFC00L 3220#define UVD_LMI_ARB_CTRL2__MIF_WR_REQ_RET_MAX_MASK 0xFFF00000L 3221//UVD_LMI_VCPU_CACHE_VMIDS_MULTI 3222#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE1_VMID__SHIFT 0x0 3223#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE2_VMID__SHIFT 0x4 3224#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE3_VMID__SHIFT 0x8 3225#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE4_VMID__SHIFT 0xc 3226#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE5_VMID__SHIFT 0x10 3227#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE6_VMID__SHIFT 0x14 3228#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE7_VMID__SHIFT 0x18 3229#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE8_VMID__SHIFT 0x1c 3230#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE1_VMID_MASK 0x0000000FL 3231#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE2_VMID_MASK 0x000000F0L 3232#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE3_VMID_MASK 0x00000F00L 3233#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE4_VMID_MASK 0x0000F000L 3234#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE5_VMID_MASK 0x000F0000L 3235#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE6_VMID_MASK 0x00F00000L 3236#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE7_VMID_MASK 0x0F000000L 3237#define UVD_LMI_VCPU_CACHE_VMIDS_MULTI__VCPU_CACHE8_VMID_MASK 0xF0000000L 3238//UVD_LMI_VCPU_NC_VMIDS_MULTI 3239#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC2_VMID__SHIFT 0x4 3240#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC3_VMID__SHIFT 0x8 3241#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC4_VMID__SHIFT 0xc 3242#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC5_VMID__SHIFT 0x10 3243#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC6_VMID__SHIFT 0x14 3244#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC7_VMID__SHIFT 0x18 3245#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC2_VMID_MASK 0x000000F0L 3246#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC3_VMID_MASK 0x00000F00L 3247#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC4_VMID_MASK 0x0000F000L 3248#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC5_VMID_MASK 0x000F0000L 3249#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC6_VMID_MASK 0x00F00000L 3250#define UVD_LMI_VCPU_NC_VMIDS_MULTI__VCPU_NC7_VMID_MASK 0x0F000000L 3251//UVD_LMI_LAT_CTRL 3252#define UVD_LMI_LAT_CTRL__SCALE__SHIFT 0x0 3253#define UVD_LMI_LAT_CTRL__MAX_START__SHIFT 0x8 3254#define UVD_LMI_LAT_CTRL__MIN_START__SHIFT 0x9 3255#define UVD_LMI_LAT_CTRL__AVG_START__SHIFT 0xa 3256#define UVD_LMI_LAT_CTRL__PERFMON_SYNC__SHIFT 0xb 3257#define UVD_LMI_LAT_CTRL__SKIP__SHIFT 0x10 3258#define UVD_LMI_LAT_CTRL__SCALE_MASK 0x000000FFL 3259#define UVD_LMI_LAT_CTRL__MAX_START_MASK 0x00000100L 3260#define UVD_LMI_LAT_CTRL__MIN_START_MASK 0x00000200L 3261#define UVD_LMI_LAT_CTRL__AVG_START_MASK 0x00000400L 3262#define UVD_LMI_LAT_CTRL__PERFMON_SYNC_MASK 0x00000800L 3263#define UVD_LMI_LAT_CTRL__SKIP_MASK 0x000F0000L 3264//UVD_LMI_LAT_CNTR 3265#define UVD_LMI_LAT_CNTR__MAX_LAT__SHIFT 0x0 3266#define UVD_LMI_LAT_CNTR__MIN_LAT__SHIFT 0x8 3267#define UVD_LMI_LAT_CNTR__MAX_LAT_MASK 0x000000FFL 3268#define UVD_LMI_LAT_CNTR__MIN_LAT_MASK 0x0000FF00L 3269//UVD_LMI_AVG_LAT_CNTR 3270#define UVD_LMI_AVG_LAT_CNTR__ENV_LOW__SHIFT 0x0 3271#define UVD_LMI_AVG_LAT_CNTR__ENV_HIGH__SHIFT 0x8 3272#define UVD_LMI_AVG_LAT_CNTR__ENV_HIT__SHIFT 0x10 3273#define UVD_LMI_AVG_LAT_CNTR__ENV_LOW_MASK 0x000000FFL 3274#define UVD_LMI_AVG_LAT_CNTR__ENV_HIGH_MASK 0x0000FF00L 3275#define UVD_LMI_AVG_LAT_CNTR__ENV_HIT_MASK 0xFFFF0000L 3276//UVD_LMI_SPH 3277#define UVD_LMI_SPH__ADDR__SHIFT 0x0 3278#define UVD_LMI_SPH__STS__SHIFT 0x1c 3279#define UVD_LMI_SPH__STS_VALID__SHIFT 0x1e 3280#define UVD_LMI_SPH__STS_OVERFLOW__SHIFT 0x1f 3281#define UVD_LMI_SPH__ADDR_MASK 0x0FFFFFFFL 3282#define UVD_LMI_SPH__STS_MASK 0x30000000L 3283#define UVD_LMI_SPH__STS_VALID_MASK 0x40000000L 3284#define UVD_LMI_SPH__STS_OVERFLOW_MASK 0x80000000L 3285//UVD_LMI_VCPU_CACHE_VMID 3286#define UVD_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID__SHIFT 0x0 3287#define UVD_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID_MASK 0x0000000FL 3288//UVD_LMI_CTRL2 3289#define UVD_LMI_CTRL2__SPH_DIS__SHIFT 0x0 3290#define UVD_LMI_CTRL2__STALL_ARB__SHIFT 0x1 3291#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2 3292#define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x3 3293#define UVD_LMI_CTRL2__CRC1_RESET__SHIFT 0x4 3294#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x7 3295#define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8 3296#define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9 3297#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb 3298#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN__SHIFT 0xd 3299#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN__SHIFT 0xe 3300#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN__SHIFT 0xf 3301#define UVD_LMI_CTRL2__RE_OFFLOAD_EN__SHIFT 0x10 3302#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT 0x11 3303#define UVD_LMI_CTRL2__CLEAR_NJ_PF_BP__SHIFT 0x19 3304#define UVD_LMI_CTRL2__NJ_MIF_GATING__SHIFT 0x1a 3305#define UVD_LMI_CTRL2__CRC1_SEL__SHIFT 0x1b 3306#define UVD_LMI_CTRL2__SPH_DIS_MASK 0x00000001L 3307#define UVD_LMI_CTRL2__STALL_ARB_MASK 0x00000002L 3308#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x00000004L 3309#define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x00000008L 3310#define UVD_LMI_CTRL2__CRC1_RESET_MASK 0x00000010L 3311#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK 0x00000080L 3312#define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L 3313#define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x00000600L 3314#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x00001800L 3315#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN_MASK 0x00002000L 3316#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN_MASK 0x00004000L 3317#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x00008000L 3318#define UVD_LMI_CTRL2__RE_OFFLOAD_EN_MASK 0x00010000L 3319#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM_MASK 0x01FE0000L 3320#define UVD_LMI_CTRL2__CLEAR_NJ_PF_BP_MASK 0x02000000L 3321#define UVD_LMI_CTRL2__NJ_MIF_GATING_MASK 0x04000000L 3322#define UVD_LMI_CTRL2__CRC1_SEL_MASK 0xF8000000L 3323//UVD_LMI_URGENT_CTRL 3324#define UVD_LMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL__SHIFT 0x0 3325#define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_STALL__SHIFT 0x1 3326#define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_URGENT__SHIFT 0x2 3327#define UVD_LMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL__SHIFT 0x8 3328#define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_STALL__SHIFT 0x9 3329#define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_URGENT__SHIFT 0xa 3330#define UVD_LMI_URGENT_CTRL__ENABLE_UMC_RD_URGENT_STALL__SHIFT 0x10 3331#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_STALL__SHIFT 0x11 3332#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_URGENT__SHIFT 0x12 3333#define UVD_LMI_URGENT_CTRL__ENABLE_UMC_WR_URGENT_STALL__SHIFT 0x18 3334#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_STALL__SHIFT 0x19 3335#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_URGENT__SHIFT 0x1a 3336#define UVD_LMI_URGENT_CTRL__ENABLE_MC_RD_URGENT_STALL_MASK 0x00000001L 3337#define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_STALL_MASK 0x00000002L 3338#define UVD_LMI_URGENT_CTRL__ASSERT_MC_RD_URGENT_MASK 0x0000003CL 3339#define UVD_LMI_URGENT_CTRL__ENABLE_MC_WR_URGENT_STALL_MASK 0x00000100L 3340#define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_STALL_MASK 0x00000200L 3341#define UVD_LMI_URGENT_CTRL__ASSERT_MC_WR_URGENT_MASK 0x00003C00L 3342#define UVD_LMI_URGENT_CTRL__ENABLE_UMC_RD_URGENT_STALL_MASK 0x00010000L 3343#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_STALL_MASK 0x00020000L 3344#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_RD_URGENT_MASK 0x003C0000L 3345#define UVD_LMI_URGENT_CTRL__ENABLE_UMC_WR_URGENT_STALL_MASK 0x01000000L 3346#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_STALL_MASK 0x02000000L 3347#define UVD_LMI_URGENT_CTRL__ASSERT_UMC_WR_URGENT_MASK 0x3C000000L 3348//UVD_LMI_CTRL 3349#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0 3350#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8 3351#define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x9 3352#define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0xb 3353#define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT 0xc 3354#define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0xd 3355#define UVD_LMI_CTRL__CRC_RESET__SHIFT 0xe 3356#define UVD_LMI_CTRL__CRC_SEL__SHIFT 0xf 3357#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15 3358#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT 0x16 3359#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT 0x17 3360#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT 0x18 3361#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT 0x19 3362#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN__SHIFT 0x1a 3363#define UVD_LMI_CTRL__MIF_LESS_OUTSTANDING_RD_REQ__SHIFT 0x1b 3364#define UVD_LMI_CTRL__RFU__SHIFT 0x1e 3365#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK 0x000000FFL 3366#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x00000100L 3367#define UVD_LMI_CTRL__REQ_MODE_MASK 0x00000200L 3368#define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000800L 3369#define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x00001000L 3370#define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x00002000L 3371#define UVD_LMI_CTRL__CRC_RESET_MASK 0x00004000L 3372#define UVD_LMI_CTRL__CRC_SEL_MASK 0x000F8000L 3373#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x00200000L 3374#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK 0x00400000L 3375#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK 0x00800000L 3376#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x01000000L 3377#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x02000000L 3378#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN_MASK 0x04000000L 3379#define UVD_LMI_CTRL__MIF_LESS_OUTSTANDING_RD_REQ_MASK 0x08000000L 3380#define UVD_LMI_CTRL__RFU_MASK 0xC0000000L 3381//UVD_LMI_STATUS 3382#define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x0 3383#define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x1 3384#define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2 3385#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x3 3386#define UVD_LMI_STATUS__UMC_READ_CLEAN__SHIFT 0x4 3387#define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 0x5 3388#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x6 3389#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE__SHIFT 0x7 3390#define UVD_LMI_STATUS__READ_CLEAN_RAW__SHIFT 0x8 3391#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x9 3392#define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0xa 3393#define UVD_LMI_STATUS__UMC_AVP_IDLE__SHIFT 0xb 3394#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN__SHIFT 0xc 3395#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN__SHIFT 0xd 3396#define UVD_LMI_STATUS__BSP0_WRITE_CLEAN__SHIFT 0x12 3397#define UVD_LMI_STATUS__BSP1_WRITE_CLEAN__SHIFT 0x13 3398#define UVD_LMI_STATUS__BSP2_WRITE_CLEAN__SHIFT 0x14 3399#define UVD_LMI_STATUS__BSP3_WRITE_CLEAN__SHIFT 0x15 3400#define UVD_LMI_STATUS__CENC_READ_CLEAN__SHIFT 0x16 3401#define UVD_LMI_STATUS__READ_CLEAN_MASK 0x00000001L 3402#define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x00000002L 3403#define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x00000004L 3404#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x00000008L 3405#define UVD_LMI_STATUS__UMC_READ_CLEAN_MASK 0x00000010L 3406#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_MASK 0x00000020L 3407#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x00000040L 3408#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE_MASK 0x00000080L 3409#define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x00000100L 3410#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x00000200L 3411#define UVD_LMI_STATUS__UMC_UVD_IDLE_MASK 0x00000400L 3412#define UVD_LMI_STATUS__UMC_AVP_IDLE_MASK 0x00000800L 3413#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN_MASK 0x00001000L 3414#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN_MASK 0x00002000L 3415#define UVD_LMI_STATUS__BSP0_WRITE_CLEAN_MASK 0x00040000L 3416#define UVD_LMI_STATUS__BSP1_WRITE_CLEAN_MASK 0x00080000L 3417#define UVD_LMI_STATUS__BSP2_WRITE_CLEAN_MASK 0x00100000L 3418#define UVD_LMI_STATUS__BSP3_WRITE_CLEAN_MASK 0x00200000L 3419#define UVD_LMI_STATUS__CENC_READ_CLEAN_MASK 0x00400000L 3420//UVD_LMI_PERFMON_CTRL 3421#define UVD_LMI_PERFMON_CTRL__PERFMON_STATE__SHIFT 0x0 3422#define UVD_LMI_PERFMON_CTRL__PERFMON_SEL__SHIFT 0x8 3423#define UVD_LMI_PERFMON_CTRL__PERFMON_STATE_MASK 0x00000003L 3424#define UVD_LMI_PERFMON_CTRL__PERFMON_SEL_MASK 0x00001F00L 3425//UVD_LMI_PERFMON_COUNT_LO 3426#define UVD_LMI_PERFMON_COUNT_LO__PERFMON_COUNT__SHIFT 0x0 3427#define UVD_LMI_PERFMON_COUNT_LO__PERFMON_COUNT_MASK 0xFFFFFFFFL 3428//UVD_LMI_PERFMON_COUNT_HI 3429#define UVD_LMI_PERFMON_COUNT_HI__PERFMON_COUNT__SHIFT 0x0 3430#define UVD_LMI_PERFMON_COUNT_HI__PERFMON_COUNT_MASK 0x0000FFFFL 3431//UVD_LMI_RBC_RB_VMID 3432#define UVD_LMI_RBC_RB_VMID__RB_VMID__SHIFT 0x0 3433#define UVD_LMI_RBC_RB_VMID__RB_VMID_MASK 0x0000000FL 3434//UVD_LMI_RBC_IB_VMID 3435#define UVD_LMI_RBC_IB_VMID__IB_VMID__SHIFT 0x0 3436#define UVD_LMI_RBC_IB_VMID__IB_VMID_MASK 0x0000000FL 3437//UVD_LMI_MC_CREDITS 3438#define UVD_LMI_MC_CREDITS__UVD_RD_CREDITS__SHIFT 0x0 3439#define UVD_LMI_MC_CREDITS__UVD_WR_CREDITS__SHIFT 0x8 3440#define UVD_LMI_MC_CREDITS__UMC_RD_CREDITS__SHIFT 0x10 3441#define UVD_LMI_MC_CREDITS__UMC_WR_CREDITS__SHIFT 0x18 3442#define UVD_LMI_MC_CREDITS__UVD_RD_CREDITS_MASK 0x0000003FL 3443#define UVD_LMI_MC_CREDITS__UVD_WR_CREDITS_MASK 0x00003F00L 3444#define UVD_LMI_MC_CREDITS__UMC_RD_CREDITS_MASK 0x003F0000L 3445#define UVD_LMI_MC_CREDITS__UMC_WR_CREDITS_MASK 0x3F000000L 3446 3447 3448// addressBlock: uvd0_uvdnpdec 3449//MDM_DMA_CMD 3450#define MDM_DMA_CMD__MDM_DMA_CMD__SHIFT 0x0 3451#define MDM_DMA_CMD__MDM_DMA_CMD_MASK 0xFFFFFFFFL 3452//MDM_DMA_STATUS 3453#define MDM_DMA_STATUS__SDB_DMA_WR_BUSY__SHIFT 0x0 3454#define MDM_DMA_STATUS__SCM_DMA_WR_BUSY__SHIFT 0x1 3455#define MDM_DMA_STATUS__SCM_DMA_RD_BUSY__SHIFT 0x2 3456#define MDM_DMA_STATUS__RB_DMA_WR_BUSY__SHIFT 0x3 3457#define MDM_DMA_STATUS__RB_DMA_RD_BUSY__SHIFT 0x4 3458#define MDM_DMA_STATUS__SDB_DMA_RD_BUSY__SHIFT 0x5 3459#define MDM_DMA_STATUS__SCLR_DMA_WR_BUSY__SHIFT 0x6 3460#define MDM_DMA_STATUS__SDB_DMA_WR_BUSY_MASK 0x00000001L 3461#define MDM_DMA_STATUS__SCM_DMA_WR_BUSY_MASK 0x00000002L 3462#define MDM_DMA_STATUS__SCM_DMA_RD_BUSY_MASK 0x00000004L 3463#define MDM_DMA_STATUS__RB_DMA_WR_BUSY_MASK 0x00000008L 3464#define MDM_DMA_STATUS__RB_DMA_RD_BUSY_MASK 0x00000010L 3465#define MDM_DMA_STATUS__SDB_DMA_RD_BUSY_MASK 0x00000020L 3466#define MDM_DMA_STATUS__SCLR_DMA_WR_BUSY_MASK 0x00000040L 3467//MDM_DMA_CTL 3468#define MDM_DMA_CTL__MDM_BYPASS__SHIFT 0x0 3469#define MDM_DMA_CTL__FOUR_CMD__SHIFT 0x1 3470#define MDM_DMA_CTL__ENCODE_MODE__SHIFT 0x2 3471#define MDM_DMA_CTL__VP9_DEC_MODE__SHIFT 0x3 3472#define MDM_DMA_CTL__SW_DRST__SHIFT 0x1f 3473#define MDM_DMA_CTL__MDM_BYPASS_MASK 0x00000001L 3474#define MDM_DMA_CTL__FOUR_CMD_MASK 0x00000002L 3475#define MDM_DMA_CTL__ENCODE_MODE_MASK 0x00000004L 3476#define MDM_DMA_CTL__VP9_DEC_MODE_MASK 0x00000008L 3477#define MDM_DMA_CTL__SW_DRST_MASK 0x80000000L 3478//MDM_ENC_PIPE_BUSY 3479#define MDM_ENC_PIPE_BUSY__IME_BUSY__SHIFT 0x0 3480#define MDM_ENC_PIPE_BUSY__SMP_BUSY__SHIFT 0x1 3481#define MDM_ENC_PIPE_BUSY__SIT_BUSY__SHIFT 0x2 3482#define MDM_ENC_PIPE_BUSY__SDB_BUSY__SHIFT 0x3 3483#define MDM_ENC_PIPE_BUSY__ENT_BUSY__SHIFT 0x4 3484#define MDM_ENC_PIPE_BUSY__ENT_HEADER_BUSY__SHIFT 0x5 3485#define MDM_ENC_PIPE_BUSY__LCM_BUSY__SHIFT 0x6 3486#define MDM_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY__SHIFT 0x7 3487#define MDM_ENC_PIPE_BUSY__MDM_RD_REF_BUSY__SHIFT 0x8 3488#define MDM_ENC_PIPE_BUSY__MDM_RD_GEN_BUSY__SHIFT 0x9 3489#define MDM_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY__SHIFT 0xa 3490#define MDM_ENC_PIPE_BUSY__MDM_WR_GEN_BUSY__SHIFT 0xb 3491#define MDM_ENC_PIPE_BUSY__MDM_EFC_BUSY__SHIFT 0xc 3492#define MDM_ENC_PIPE_BUSY__MDM_EFC_PROGRAM_BUSY__SHIFT 0xd 3493#define MDM_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY__SHIFT 0x10 3494#define MDM_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY__SHIFT 0x11 3495#define MDM_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY__SHIFT 0x12 3496#define MDM_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY__SHIFT 0x13 3497#define MDM_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY__SHIFT 0x14 3498#define MDM_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY__SHIFT 0x15 3499#define MDM_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY__SHIFT 0x16 3500#define MDM_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY__SHIFT 0x17 3501#define MDM_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY__SHIFT 0x18 3502#define MDM_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY__SHIFT 0x19 3503#define MDM_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY__SHIFT 0x1a 3504#define MDM_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY__SHIFT 0x1b 3505#define MDM_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY__SHIFT 0x1c 3506#define MDM_ENC_PIPE_BUSY__IME_BUSY_MASK 0x00000001L 3507#define MDM_ENC_PIPE_BUSY__SMP_BUSY_MASK 0x00000002L 3508#define MDM_ENC_PIPE_BUSY__SIT_BUSY_MASK 0x00000004L 3509#define MDM_ENC_PIPE_BUSY__SDB_BUSY_MASK 0x00000008L 3510#define MDM_ENC_PIPE_BUSY__ENT_BUSY_MASK 0x00000010L 3511#define MDM_ENC_PIPE_BUSY__ENT_HEADER_BUSY_MASK 0x00000020L 3512#define MDM_ENC_PIPE_BUSY__LCM_BUSY_MASK 0x00000040L 3513#define MDM_ENC_PIPE_BUSY__MDM_RD_CUR_BUSY_MASK 0x00000080L 3514#define MDM_ENC_PIPE_BUSY__MDM_RD_REF_BUSY_MASK 0x00000100L 3515#define MDM_ENC_PIPE_BUSY__MDM_RD_GEN_BUSY_MASK 0x00000200L 3516#define MDM_ENC_PIPE_BUSY__MDM_WR_RECON_BUSY_MASK 0x00000400L 3517#define MDM_ENC_PIPE_BUSY__MDM_WR_GEN_BUSY_MASK 0x00000800L 3518#define MDM_ENC_PIPE_BUSY__MDM_EFC_BUSY_MASK 0x00001000L 3519#define MDM_ENC_PIPE_BUSY__MDM_EFC_PROGRAM_BUSY_MASK 0x00002000L 3520#define MDM_ENC_PIPE_BUSY__MIF_RD_CUR_BUSY_MASK 0x00010000L 3521#define MDM_ENC_PIPE_BUSY__MIF_RD_REF0_BUSY_MASK 0x00020000L 3522#define MDM_ENC_PIPE_BUSY__MIF_WR_GEN0_BUSY_MASK 0x00040000L 3523#define MDM_ENC_PIPE_BUSY__MIF_RD_GEN0_BUSY_MASK 0x00080000L 3524#define MDM_ENC_PIPE_BUSY__MIF_WR_GEN1_BUSY_MASK 0x00100000L 3525#define MDM_ENC_PIPE_BUSY__MIF_RD_GEN1_BUSY_MASK 0x00200000L 3526#define MDM_ENC_PIPE_BUSY__MIF_WR_BSP0_BUSY_MASK 0x00400000L 3527#define MDM_ENC_PIPE_BUSY__MIF_WR_BSP1_BUSY_MASK 0x00800000L 3528#define MDM_ENC_PIPE_BUSY__MIF_RD_BSD0_BUSY_MASK 0x01000000L 3529#define MDM_ENC_PIPE_BUSY__MIF_RD_BSD1_BUSY_MASK 0x02000000L 3530#define MDM_ENC_PIPE_BUSY__MIF_RD_BSD2_BUSY_MASK 0x04000000L 3531#define MDM_ENC_PIPE_BUSY__MIF_RD_BSD3_BUSY_MASK 0x08000000L 3532#define MDM_ENC_PIPE_BUSY__MIF_RD_BSD4_BUSY_MASK 0x10000000L 3533//MDM_WIG_PIPE_BUSY 3534#define MDM_WIG_PIPE_BUSY__WIG_TBE_BUSY__SHIFT 0x0 3535#define MDM_WIG_PIPE_BUSY__WIG_ENT_BUSY__SHIFT 0x1 3536#define MDM_WIG_PIPE_BUSY__WIG_ENT_HEADER_BUSY__SHIFT 0x2 3537#define MDM_WIG_PIPE_BUSY__WIG_ENT_HEADER_FIFO_FULL__SHIFT 0x3 3538#define MDM_WIG_PIPE_BUSY__LCM_BUSY__SHIFT 0x4 3539#define MDM_WIG_PIPE_BUSY__MDM_RD_CUR_BUSY__SHIFT 0x5 3540#define MDM_WIG_PIPE_BUSY__MDM_RD_REF_BUSY__SHIFT 0x6 3541#define MDM_WIG_PIPE_BUSY__MDM_RD_GEN_BUSY__SHIFT 0x7 3542#define MDM_WIG_PIPE_BUSY__MDM_WR_RECON_BUSY__SHIFT 0x8 3543#define MDM_WIG_PIPE_BUSY__MDM_WR_GEN_BUSY__SHIFT 0x9 3544#define MDM_WIG_PIPE_BUSY__MIF_RD_CUR_BUSY__SHIFT 0xa 3545#define MDM_WIG_PIPE_BUSY__MIF_RD_REF0_BUSY__SHIFT 0xb 3546#define MDM_WIG_PIPE_BUSY__MIF_WR_GEN0_BUSY__SHIFT 0xc 3547#define MDM_WIG_PIPE_BUSY__MIF_RD_GEN0_BUSY__SHIFT 0xd 3548#define MDM_WIG_PIPE_BUSY__MIF_WR_GEN1_BUSY__SHIFT 0xe 3549#define MDM_WIG_PIPE_BUSY__MIF_RD_GEN1_BUSY__SHIFT 0xf 3550#define MDM_WIG_PIPE_BUSY__MIF_WR_BSP0_BUSY__SHIFT 0x10 3551#define MDM_WIG_PIPE_BUSY__MIF_WR_BSP1_BUSY__SHIFT 0x11 3552#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD0_BUSY__SHIFT 0x12 3553#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD1_BUSY__SHIFT 0x13 3554#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD2_BUSY__SHIFT 0x14 3555#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD3_BUSY__SHIFT 0x15 3556#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD4_BUSY__SHIFT 0x16 3557#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD5_BUSY__SHIFT 0x17 3558#define MDM_WIG_PIPE_BUSY__MIF_WR_BSP2_BUSY__SHIFT 0x18 3559#define MDM_WIG_PIPE_BUSY__MIF_WR_BSP3_BUSY__SHIFT 0x19 3560#define MDM_WIG_PIPE_BUSY__LCM_BSP0_NOT_EMPTY__SHIFT 0x1a 3561#define MDM_WIG_PIPE_BUSY__LCM_BSP1_NOT_EMPTY__SHIFT 0x1b 3562#define MDM_WIG_PIPE_BUSY__LCM_BSP2_NOT_EMPTY__SHIFT 0x1c 3563#define MDM_WIG_PIPE_BUSY__LCM_BSP3_NOT_EMPTY__SHIFT 0x1d 3564#define MDM_WIG_PIPE_BUSY__WIG_TBE_BUSY_MASK 0x00000001L 3565#define MDM_WIG_PIPE_BUSY__WIG_ENT_BUSY_MASK 0x00000002L 3566#define MDM_WIG_PIPE_BUSY__WIG_ENT_HEADER_BUSY_MASK 0x00000004L 3567#define MDM_WIG_PIPE_BUSY__WIG_ENT_HEADER_FIFO_FULL_MASK 0x00000008L 3568#define MDM_WIG_PIPE_BUSY__LCM_BUSY_MASK 0x00000010L 3569#define MDM_WIG_PIPE_BUSY__MDM_RD_CUR_BUSY_MASK 0x00000020L 3570#define MDM_WIG_PIPE_BUSY__MDM_RD_REF_BUSY_MASK 0x00000040L 3571#define MDM_WIG_PIPE_BUSY__MDM_RD_GEN_BUSY_MASK 0x00000080L 3572#define MDM_WIG_PIPE_BUSY__MDM_WR_RECON_BUSY_MASK 0x00000100L 3573#define MDM_WIG_PIPE_BUSY__MDM_WR_GEN_BUSY_MASK 0x00000200L 3574#define MDM_WIG_PIPE_BUSY__MIF_RD_CUR_BUSY_MASK 0x00000400L 3575#define MDM_WIG_PIPE_BUSY__MIF_RD_REF0_BUSY_MASK 0x00000800L 3576#define MDM_WIG_PIPE_BUSY__MIF_WR_GEN0_BUSY_MASK 0x00001000L 3577#define MDM_WIG_PIPE_BUSY__MIF_RD_GEN0_BUSY_MASK 0x00002000L 3578#define MDM_WIG_PIPE_BUSY__MIF_WR_GEN1_BUSY_MASK 0x00004000L 3579#define MDM_WIG_PIPE_BUSY__MIF_RD_GEN1_BUSY_MASK 0x00008000L 3580#define MDM_WIG_PIPE_BUSY__MIF_WR_BSP0_BUSY_MASK 0x00010000L 3581#define MDM_WIG_PIPE_BUSY__MIF_WR_BSP1_BUSY_MASK 0x00020000L 3582#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD0_BUSY_MASK 0x00040000L 3583#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD1_BUSY_MASK 0x00080000L 3584#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD2_BUSY_MASK 0x00100000L 3585#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD3_BUSY_MASK 0x00200000L 3586#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD4_BUSY_MASK 0x00400000L 3587#define MDM_WIG_PIPE_BUSY__MIF_RD_BSD5_BUSY_MASK 0x00800000L 3588#define MDM_WIG_PIPE_BUSY__MIF_WR_BSP2_BUSY_MASK 0x01000000L 3589#define MDM_WIG_PIPE_BUSY__MIF_WR_BSP3_BUSY_MASK 0x02000000L 3590#define MDM_WIG_PIPE_BUSY__LCM_BSP0_NOT_EMPTY_MASK 0x04000000L 3591#define MDM_WIG_PIPE_BUSY__LCM_BSP1_NOT_EMPTY_MASK 0x08000000L 3592#define MDM_WIG_PIPE_BUSY__LCM_BSP2_NOT_EMPTY_MASK 0x10000000L 3593#define MDM_WIG_PIPE_BUSY__LCM_BSP3_NOT_EMPTY_MASK 0x20000000L 3594 3595 3596// addressBlock: lmi_adp_indirect 3597//UVD_LMI_CRC0 3598#define UVD_LMI_CRC0__CRC32__SHIFT 0x0 3599#define UVD_LMI_CRC0__CRC32_MASK 0xFFFFFFFFL 3600//UVD_LMI_CRC1 3601#define UVD_LMI_CRC1__CRC32__SHIFT 0x0 3602#define UVD_LMI_CRC1__CRC32_MASK 0xFFFFFFFFL 3603//UVD_LMI_CRC2 3604#define UVD_LMI_CRC2__CRC32__SHIFT 0x0 3605#define UVD_LMI_CRC2__CRC32_MASK 0xFFFFFFFFL 3606//UVD_LMI_CRC3 3607#define UVD_LMI_CRC3__CRC32__SHIFT 0x0 3608#define UVD_LMI_CRC3__CRC32_MASK 0xFFFFFFFFL 3609 3610 3611#endif 3612