Searched refs:UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT (Results 1 - 4 of 4) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h62 #define UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT 0x14 macro
H A Dvcn_2_0_0_sh_mask.h1497 #define UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT 0x14 macro
H A Dvcn_2_5_sh_mask.h1500 #define UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT 0x14 macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_vcn_v1_0.c773 | 2 << UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT);

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