Searched refs:UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT (Results 1 - 5 of 5) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_vcn_v1_0.c696 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
711 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
749 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
H A Damdgpu_vcn_v2_0.c669 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
684 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
723 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h29 #define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 0x0 macro
H A Dvcn_2_0_0_sh_mask.h1462 #define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 0x0 macro
H A Dvcn_2_5_sh_mask.h1465 #define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 0x0 macro

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