Searched refs:UVD_MPC_SET_MUXA0__VARA_2__SHIFT (Results 1 - 11 of 11) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_vcn_v1_0.c828 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
1011 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
H A Damdgpu_vcn_v2_0.c799 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
923 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
H A Damdgpu_vcn_v2_5.c807 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
950 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
H A Duvd_4_0_sh_mask.h503 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0x0000000c macro
H A Duvd_6_0_sh_mask.h522 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc macro
H A Duvd_7_0_sh_mask.h602 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc macro
H A Duvd_5_0_sh_mask.h520 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc macro
H A Duvd_4_2_sh_mask.h488 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h1109 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc macro
H A Dvcn_2_0_0_sh_mask.h2615 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc macro
H A Dvcn_2_5_sh_mask.h2850 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc macro

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