Searched refs:UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT (Results 1 - 13 of 13) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_vcn_v1_0.c991 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
1046 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
H A Damdgpu_uvd_v7_0.c876 (uint32_t)((0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
991 (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
H A Damdgpu_uvd_v6_0.c746 (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
H A Damdgpu_vcn_v2_0.c787 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
H A Damdgpu_vcn_v2_5.c795 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
H A Duvd_4_0_sh_mask.h353 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x00000000 macro
H A Duvd_6_0_sh_mask.h386 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0 macro
H A Duvd_7_0_sh_mask.h507 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0 macro
H A Duvd_5_0_sh_mask.h384 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0 macro
H A Duvd_4_2_sh_mask.h352 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0 macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h1029 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0 macro
H A Dvcn_2_0_0_sh_mask.h2398 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0 macro
H A Dvcn_2_5_sh_mask.h3349 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0 macro

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