Searched refs:UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK (Results 1 - 13 of 13) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_vcn_v1_0.c810 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
992 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
1047 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
H A Damdgpu_vcn_v2_0.c781 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
909 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
H A Damdgpu_vcn_v2_5.c789 tmp = (0x8 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
936 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
H A Damdgpu_uvd_v7_0.c877 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
992 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
H A Damdgpu_uvd_v6_0.c747 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
H A Duvd_4_0_sh_mask.h350 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x00000100L macro
H A Duvd_6_0_sh_mask.h387 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x100 macro
H A Duvd_7_0_sh_mask.h522 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x00000100L macro
H A Duvd_5_0_sh_mask.h385 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x100 macro
H A Duvd_4_2_sh_mask.h353 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x100 macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h1044 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x00000100L macro
H A Dvcn_2_0_0_sh_mask.h2415 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x00000100L macro
H A Dvcn_2_5_sh_mask.h3366 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x00000100L macro

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