Searched refs:UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT_MASK (Results 1 - 3 of 3) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h769 #define UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT_MASK 0x00000010L macro
H A Dvcn_2_0_0_sh_mask.h752 #define UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT_MASK 0x00000010L macro
H A Dvcn_2_5_sh_mask.h755 #define UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT_MASK 0x00000010L macro

Completed in 225 milliseconds