Searched refs:UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT (Results 1 - 8 of 8) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
H A Duvd_4_0_sh_mask.h257 #define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x00000000 macro
H A Duvd_6_0_sh_mask.h50 #define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0 macro
H A Duvd_7_0_sh_mask.h122 #define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0 macro
H A Duvd_5_0_sh_mask.h50 #define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0 macro
H A Duvd_4_2_sh_mask.h50 #define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0 macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h312 #define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0 macro
H A Dvcn_2_0_0_sh_mask.h3172 #define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0 macro
H A Dvcn_2_5_sh_mask.h2201 #define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0 macro

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