Searched refs:THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT (Results 1 - 8 of 8) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/thm/
H A Dthm_11_0_2_sh_mask.h49 #define THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4 macro
H A Dthm_10_0_sh_mask.h130 #define THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4 macro
H A Dthm_9_0_sh_mask.h274 #define THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4 macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
H A Damdgpu_vega12_thermal.c217 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
H A Damdgpu_vega20_thermal.c287 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
H A Damdgpu_vega10_thermal.c449 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/powerplay/
H A Damdgpu_smu_v11_0.c1194 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/smu/
H A Dsmu_8_0_sh_mask.h152 #define THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4 macro

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