1/* $NetBSD: thm_11_0_2_sh_mask.h,v 1.2 2021/12/18 23:45:24 riastradh Exp $ */ 2 3/* 4 * Copyright (C) 2018 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24#ifndef _thm_11_0_2_SH_MASK_HEADER 25#define _thm_11_0_2_SH_MASK_HEADER 26 27 28//CG_MULT_THERMAL_STATUS 29#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP__SHIFT 0x0 30#define CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT 0x9 31#define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP_MASK 0x000001FFL 32#define CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK 0x0003FE00L 33#define CG_FDO_CTRL2__TMIN__SHIFT 0x0 34#define CG_FDO_CTRL2__TMIN_MASK 0x000000FFL 35#define CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT 0xb 36#define CG_FDO_CTRL2__FDO_PWM_MODE_MASK 0x00003800L 37#define CG_FDO_CTRL1__FMAX_DUTY100__SHIFT 0x0 38#define CG_FDO_CTRL1__FMAX_DUTY100_MASK 0x000000FFL 39#define CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT 0x0 40#define CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK 0x000000FFL 41#define CG_TACH_CTRL__TARGET_PERIOD__SHIFT 0x3 42#define CG_TACH_CTRL__TARGET_PERIOD_MASK 0xFFFFFFF8L 43 44//THM_THERMAL_INT_ENA 45#define THM_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT 0x0 46#define THM_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT 0x1 47#define THM_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT 0x2 48#define THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT 0x3 49#define THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4 50#define THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT 0x5 51#define THM_THERMAL_INT_ENA__THERM_INTH_SET_MASK 0x00000001L 52#define THM_THERMAL_INT_ENA__THERM_INTL_SET_MASK 0x00000002L 53#define THM_THERMAL_INT_ENA__THERM_TRIGGER_SET_MASK 0x00000004L 54#define THM_THERMAL_INT_ENA__THERM_INTH_CLR_MASK 0x00000008L 55#define THM_THERMAL_INT_ENA__THERM_INTL_CLR_MASK 0x00000010L 56#define THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR_MASK 0x00000020L 57//THM_THERMAL_INT_CTRL 58#define THM_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT 0x0 59#define THM_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT 0x8 60#define THM_THERMAL_INT_CTRL__TEMP_THRESHOLD__SHIFT 0x10 61#define THM_THERMAL_INT_CTRL__THERM_INTH_MASK__SHIFT 0x18 62#define THM_THERMAL_INT_CTRL__THERM_INTL_MASK__SHIFT 0x19 63#define THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK__SHIFT 0x1a 64#define THM_THERMAL_INT_CTRL__THERM_PROCHOT_MASK__SHIFT 0x1b 65#define THM_THERMAL_INT_CTRL__THERM_IH_HW_ENA__SHIFT 0x1c 66#define THM_THERMAL_INT_CTRL__MAX_IH_CREDIT__SHIFT 0x1d 67#define THM_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK 0x000000FFL 68#define THM_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK 0x0000FF00L 69#define THM_THERMAL_INT_CTRL__TEMP_THRESHOLD_MASK 0x00FF0000L 70#define THM_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK 0x01000000L 71#define THM_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK 0x02000000L 72#define THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK 0x04000000L 73#define THM_THERMAL_INT_CTRL__THERM_PROCHOT_MASK_MASK 0x08000000L 74#define THM_THERMAL_INT_CTRL__THERM_IH_HW_ENA_MASK 0x10000000L 75#define THM_THERMAL_INT_CTRL__MAX_IH_CREDIT_MASK 0xE0000000L 76 77//THM_TCON_THERM_TRIP 78#define THM_TCON_THERM_TRIP__CTF_PAD_POLARITY__SHIFT 0x0 79#define THM_TCON_THERM_TRIP__THERM_TP__SHIFT 0x1 80#define THM_TCON_THERM_TRIP__CTF_THRESHOLD_EXCEEDED__SHIFT 0x2 81#define THM_TCON_THERM_TRIP__THERM_TP_SENSE__SHIFT 0x3 82#define THM_TCON_THERM_TRIP__RSVD2__SHIFT 0x4 83#define THM_TCON_THERM_TRIP__THERM_TP_EN__SHIFT 0x5 84#define THM_TCON_THERM_TRIP__THERM_TP_LMT__SHIFT 0x6 85#define THM_TCON_THERM_TRIP__RSVD3__SHIFT 0xe 86#define THM_TCON_THERM_TRIP__SW_THERM_TP__SHIFT 0x1f 87#define THM_TCON_THERM_TRIP__CTF_PAD_POLARITY_MASK 0x00000001L 88#define THM_TCON_THERM_TRIP__THERM_TP_MASK 0x00000002L 89#define THM_TCON_THERM_TRIP__CTF_THRESHOLD_EXCEEDED_MASK 0x00000004L 90#define THM_TCON_THERM_TRIP__THERM_TP_SENSE_MASK 0x00000008L 91#define THM_TCON_THERM_TRIP__RSVD2_MASK 0x00000010L 92#define THM_TCON_THERM_TRIP__THERM_TP_EN_MASK 0x00000020L 93#define THM_TCON_THERM_TRIP__THERM_TP_LMT_MASK 0x00003FC0L 94#define THM_TCON_THERM_TRIP__RSVD3_MASK 0x7FFFC000L 95#define THM_TCON_THERM_TRIP__SW_THERM_TP_MASK 0x80000000L 96 97#endif 98 99