Searched refs:THM_CLK_CNTL__CMON_CLK_SEL_MASK (Results 1 - 11 of 11) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
H A Damdgpu_ci_baco.c124 { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__CMON_CLK_SEL_MASK, THM_CLK_CNTL__CMON_CLK_SEL__SHIFT, 0, 0x2 },
H A Damdgpu_fiji_baco.c108 { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__CMON_CLK_SEL_MASK, THM_CLK_CNTL__CMON_CLK_SEL__SHIFT, 0, 0x1 },
H A Damdgpu_polaris_baco.c103 { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__CMON_CLK_SEL_MASK, THM_CLK_CNTL__CMON_CLK_SEL__SHIFT, 0, 0x1 },
H A Damdgpu_tonga_baco.c116 { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, THM_CLK_CNTL__CMON_CLK_SEL_MASK, THM_CLK_CNTL__CMON_CLK_SEL__SHIFT, 0, 0x1 },
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_cik.c1755 data &= ~(THM_CLK_CNTL__CMON_CLK_SEL_MASK |
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/smu/
H A Dsmu_7_0_0_sh_mask.h265 #define THM_CLK_CNTL__CMON_CLK_SEL_MASK 0xff macro
H A Dsmu_7_1_1_sh_mask.h263 #define THM_CLK_CNTL__CMON_CLK_SEL_MASK 0xff macro
H A Dsmu_7_1_3_sh_mask.h291 #define THM_CLK_CNTL__CMON_CLK_SEL_MASK 0xff macro
H A Dsmu_7_1_2_sh_mask.h263 #define THM_CLK_CNTL__CMON_CLK_SEL_MASK 0xff macro
H A Dsmu_7_1_0_sh_mask.h261 #define THM_CLK_CNTL__CMON_CLK_SEL_MASK 0xff macro
H A Dsmu_7_0_1_sh_mask.h263 #define THM_CLK_CNTL__CMON_CLK_SEL_MASK 0xff macro

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