| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostLegalizerCombiner.cpp | 255 int64_t ShiftImm; local
258 m_OneNonDBGUse(m_any_of(m_GAShr(m_Reg(ShiftSrc), m_ICst(ShiftImm)),
259 m_GLShr(m_Reg(ShiftSrc), m_ICst(ShiftImm))))))
261 if (ShiftImm < 0 || ShiftImm + Width > Ty.getSizeInBits())
264 auto Cst1 = B.buildConstant(Ty, ShiftImm);
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| H A D | AArch64InstructionSelector.cpp | 1632 Optional<int64_t> ShiftImm = getVectorShiftImm(Reg, MRI);
1633 if (!ShiftImm)
1636 int64_t Imm = *ShiftImm;
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| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsExpandPseudo.cpp | 181 const unsigned ShiftImm = local
185 .addImm(ShiftImm);
188 .addImm(ShiftImm);
557 const unsigned ShiftImm = SEOp == Mips::SEH ? 16 : 24; local
560 .addImm(ShiftImm);
563 .addImm(ShiftImm);
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| H A D | MipsISelLowering.cpp | 1634 int64_t ShiftImm = 32 - (Size * 8);
1636 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm);
1637 BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm);
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| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 212 uint64_t ShiftImm, bool SetFlags = false,
216 uint64_t ShiftImm, bool SetFlags = false,
243 AArch64_AM::ShiftExtendType ShiftType, uint64_t ShiftImm,
250 unsigned RHSReg, uint64_t ShiftImm);
1325 unsigned ShiftImm; local
1327 ShiftImm = 0;
1329 ShiftImm = 12;
1358 .addImm(getShifterImm(AArch64_AM::LSL, ShiftImm));
1365 uint64_t ShiftImm, bool SetFlags,
1375 if (ShiftImm >
1362 emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg, unsigned RHSReg, AArch64_AM::ShiftExtendType ShiftType, uint64_t ShiftImm, bool SetFlags, bool WantResult) argument
1404 emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg, unsigned RHSReg, AArch64_AM::ShiftExtendType ExtType, uint64_t ShiftImm, bool SetFlags, bool WantResult) argument
1555 emitSubs_rs(MVT RetVT, unsigned LHSReg, unsigned RHSReg, AArch64_AM::ShiftExtendType ShiftType, uint64_t ShiftImm, bool WantResult) argument
1686 emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT, unsigned LHSReg, unsigned RHSReg, uint64_t ShiftImm) argument
[all...] |
| H A D | AArch64ISelDAGToDAG.cpp | 1871 uint64_t ShiftImm; local
1872 if (!isOpcWithIntImmediate(Op.getNode(), ISD::SRL, ShiftImm) &&
1873 !isOpcWithIntImmediate(Op.getNode(), ISD::SRA, ShiftImm))
1877 if (ShiftImm + Width > BitWidth)
1882 Immr = ShiftImm;
1883 Imms = ShiftImm + Width - 1;
1895 // SRL Value2, ShiftImm
1897 // with MaskImm >> ShiftImm to search for the bit width.
1901 // UBFM Value, ShiftImm, BitWide + SrlImm -1
2008 uint64_t ShiftImm;
[all...] |
| H A D | AArch64ISelLowering.cpp | 14665 unsigned ShiftImm = N->getConstantOperandVal(1); local
14666 assert(OpScalarSize > ShiftImm && "Invalid shift imm");
14668 APInt ShiftedOutBits = APInt::getLowBitsSet(OpScalarSize, ShiftImm);
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| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 853 unsigned ShiftImm; // shift for OffsetReg. member in struct:__anon2324::ARMOperand::MemoryOp
863 unsigned ShiftImm; member in struct:__anon2324::ARMOperand::PostIdxRegOp
875 unsigned ShiftImm; member in struct:__anon2324::ARMOperand::RegShiftedRegOp
881 unsigned ShiftImm; member in struct:__anon2324::ARMOperand::RegShiftedImmOp
1691 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1710 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1889 (Memory.ShiftType != ARM_AM::uxtw || Memory.ShiftImm != shift))
2551 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
2560 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
3639 CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, unsigned ShiftReg, unsigned ShiftImm, SMLoc S, SMLoc E) argument
3653 CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, unsigned ShiftImm, SMLoc S, SMLoc E) argument
3803 CreateMem(unsigned BaseRegNum, const MCExpr *OffsetImm, unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType, unsigned ShiftImm, unsigned Alignment, bool isNegative, SMLoc S, SMLoc E, SMLoc AlignmentLoc = SMLoc()) argument
3821 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy, unsigned ShiftImm, SMLoc S, SMLoc E) argument
5646 unsigned ShiftImm = 0; local
5986 unsigned ShiftImm = 0; local
[all...] |
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 2775 unsigned ShiftImm; local
2778 ShiftImm = CI->getZExtValue();
2782 if (ShiftImm == 0 || ShiftImm >=32)
2806 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm));
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| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMMCCodeEmitter.cpp | 947 // This value is encoded as follows, if ShiftImm is the value within those
948 // ranges then the encoding szimm5 = ShiftImm + size, where size is either 8
951 unsigned Size, ShiftImm; local
968 ShiftImm = MI.getOperand(OpIdx).getImm();
969 return Size + ShiftImm;
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| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCMIPeephole.cpp | 666 unsigned ShiftImm = DefMI->getOperand(3).getImm(); local
669 unsigned NewElem = (SplatImm + ShiftImm) & 0x3;
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| /netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAG.cpp | 5620 const APInt &ShiftImm = N2C->getAPIntValue();
5621 return getVScale(DL, VT, MulImm << ShiftImm);
|