Searched refs:SOFT_REGISTERS_TABLE_15__DisplayPhy7Config_MASK (Results 1 - 5 of 5) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/smu/
H A Dsmu_7_1_1_sh_mask.h2717 #define SOFT_REGISTERS_TABLE_15__DisplayPhy7Config_MASK 0xff00 macro
H A Dsmu_7_1_3_sh_mask.h3411 #define SOFT_REGISTERS_TABLE_15__DisplayPhy7Config_MASK 0xff00 macro
H A Dsmu_7_1_2_sh_mask.h3743 #define SOFT_REGISTERS_TABLE_15__DisplayPhy7Config_MASK 0xff00 macro
H A Dsmu_7_1_0_sh_mask.h3579 #define SOFT_REGISTERS_TABLE_15__DisplayPhy7Config_MASK 0xff00 macro
H A Dsmu_7_0_1_sh_mask.h3583 #define SOFT_REGISTERS_TABLE_15__DisplayPhy7Config_MASK 0xff00 macro

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