Searched refs:SOFT_REGISTERS_TABLE_15__DisplayPhy6Config_MASK (Results 1 - 5 of 5) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/smu/
H A Dsmu_7_1_1_sh_mask.h2719 #define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config_MASK 0xff0000 macro
H A Dsmu_7_1_3_sh_mask.h3413 #define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config_MASK 0xff0000 macro
H A Dsmu_7_1_2_sh_mask.h3745 #define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config_MASK 0xff0000 macro
H A Dsmu_7_1_0_sh_mask.h3581 #define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config_MASK 0xff0000 macro
H A Dsmu_7_0_1_sh_mask.h3585 #define SOFT_REGISTERS_TABLE_15__DisplayPhy6Config_MASK 0xff0000 macro

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