Searched refs:SOFT_REGISTERS_TABLE_14__DisplayPhy4Config_MASK (Results 1 - 5 of 5) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/smu/
H A Dsmu_7_1_1_sh_mask.h2707 #define SOFT_REGISTERS_TABLE_14__DisplayPhy4Config_MASK 0xff macro
H A Dsmu_7_1_3_sh_mask.h3401 #define SOFT_REGISTERS_TABLE_14__DisplayPhy4Config_MASK 0xff macro
H A Dsmu_7_1_2_sh_mask.h3733 #define SOFT_REGISTERS_TABLE_14__DisplayPhy4Config_MASK 0xff macro
H A Dsmu_7_1_0_sh_mask.h3569 #define SOFT_REGISTERS_TABLE_14__DisplayPhy4Config_MASK 0xff macro
H A Dsmu_7_0_1_sh_mask.h3573 #define SOFT_REGISTERS_TABLE_14__DisplayPhy4Config_MASK 0xff macro

Completed in 482 milliseconds