Searched refs:Ra (Results 1 - 20 of 20) sorted by relevance

/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64PBQPRegAlloc.h30 // parity(Rd) == parity(Ra).
32 bool addIntraChainConstraint(PBQPRAGraph &G, unsigned Rd, unsigned Ra);
35 void addInterChainConstraint(PBQPRAGraph &G, unsigned Rd, unsigned Ra);
H A DAArch64PBQPRegAlloc.cpp159 unsigned Ra) {
160 if (Rd == Ra)
165 if (Register::isPhysicalRegister(Rd) || Register::isPhysicalRegister(Ra)) {
168 LLVM_DEBUG(dbgs() << "Ra is a physical reg:"
169 << Register::isPhysicalRegister(Ra) << '\n');
174 PBQPRAGraph::NodeId node2 = G.getMetadata().getNodeIdForVReg(Ra);
187 const LiveInterval &la = LIs.getInterval(Ra);
243 unsigned Ra) {
247 if (Chains.count(Ra)) {
248 if (Rd != Ra) {
158 addIntraChainConstraint(PBQPRAGraph &G, unsigned Rd, unsigned Ra) argument
242 addInterChainConstraint(PBQPRAGraph &G, unsigned Rd, unsigned Ra) argument
363 Register Ra = MI.getOperand(3).getReg(); local
[all...]
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMCCodeEmitter.cpp114 MCRegister Ra; local
117 Ra = RISCV::X6;
120 Ra = MI.getOperand(0).getReg();
123 Ra = RISCV::X1;
126 Ra = MI.getOperand(0).getReg();
134 // Emit AUIPC Ra, Func with R_RISCV_CALL relocation type.
136 .addReg(Ra)
143 // Emit JALR X0, Ra, 0
144 TmpInst = MCInstBuilder(RISCV::JALR).addReg(RISCV::X0).addReg(Ra).addImm(0);
146 // Emit JALR Ra, R
[all...]
/netbsd-current/external/gpl3/binutils/dist/opcodes/
H A Dd30v-opc.c348 #define Ra (UNUSED + 1) macro
350 #define Ra2 (Ra + 1)
423 { SHORT_M, 0, { Ra, ATPAR, Rb, Rc } }, /* Ra,@(Rb,Rc) */
424 { SHORT_M, 1, { Ra, ATPAR, Rb, PLUS, Rc } }, /* Ra,@(Rb+,Rc) */
425 { SHORT_M, 2, { Ra, ATPAR, Rb, IMM6 } }, /* Ra,@(Rb,imm6) */
426 { SHORT_M, 3, { Ra, ATPAR, Rb, MINUS, Rc } }, /* Ra,
[all...]
H A Daarch64-tbl.h3521 CORE_INSN ("madd", 0x1b000000, 0x7fe08000, dp_3src, 0, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMER, F_HAS_ALIAS | F_SF),
3523 CORE_INSN ("msub", 0x1b008000, 0x7fe08000, dp_3src, 0, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMER, F_HAS_ALIAS | F_SF),
3525 CORE_INSN ("smaddl",0x9b200000, 0xffe08000, dp_3src, 0, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS),
3527 CORE_INSN ("smsubl",0x9b208000, 0xffe08000, dp_3src, 0, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS),
3530 CORE_INSN ("umaddl",0x9ba00000, 0xffe08000, dp_3src, 0, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS),
3532 CORE_INSN ("umsubl",0x9ba08000, 0xffe08000, dp_3src, 0, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS),
5463 Y(INT_REG, regno, "Ra", 0, F(FLD_Ra), "an integer register") \
/netbsd-current/external/gpl3/gdb.old/dist/opcodes/
H A Dd30v-opc.c348 #define Ra (UNUSED + 1) macro
350 #define Ra2 (Ra + 1)
423 { SHORT_M, 0, { Ra, ATPAR, Rb, Rc } }, /* Ra,@(Rb,Rc) */
424 { SHORT_M, 1, { Ra, ATPAR, Rb, PLUS, Rc } }, /* Ra,@(Rb+,Rc) */
425 { SHORT_M, 2, { Ra, ATPAR, Rb, IMM6 } }, /* Ra,@(Rb,imm6) */
426 { SHORT_M, 3, { Ra, ATPAR, Rb, MINUS, Rc } }, /* Ra,
[all...]
H A Daarch64-tbl.h3345 CORE_INSN ("madd", 0x1b000000, 0x7fe08000, dp_3src, 0, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMER, F_HAS_ALIAS | F_SF),
3347 CORE_INSN ("msub", 0x1b008000, 0x7fe08000, dp_3src, 0, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMER, F_HAS_ALIAS | F_SF),
3349 CORE_INSN ("smaddl",0x9b200000, 0xffe08000, dp_3src, 0, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS),
3351 CORE_INSN ("smsubl",0x9b208000, 0xffe08000, dp_3src, 0, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS),
3354 CORE_INSN ("umaddl",0x9ba00000, 0xffe08000, dp_3src, 0, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS),
3356 CORE_INSN ("umsubl",0x9ba08000, 0xffe08000, dp_3src, 0, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS),
5155 Y(INT_REG, regno, "Ra", 0, F(FLD_Ra), "an integer register") \
/netbsd-current/external/gpl3/gdb/dist/opcodes/
H A Dd30v-opc.c348 #define Ra (UNUSED + 1) macro
350 #define Ra2 (Ra + 1)
423 { SHORT_M, 0, { Ra, ATPAR, Rb, Rc } }, /* Ra,@(Rb,Rc) */
424 { SHORT_M, 1, { Ra, ATPAR, Rb, PLUS, Rc } }, /* Ra,@(Rb+,Rc) */
425 { SHORT_M, 2, { Ra, ATPAR, Rb, IMM6 } }, /* Ra,@(Rb,imm6) */
426 { SHORT_M, 3, { Ra, ATPAR, Rb, MINUS, Rc } }, /* Ra,
[all...]
H A Daarch64-tbl.h3535 CORE_INSN ("madd", 0x1b000000, 0x7fe08000, dp_3src, 0, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMER, F_HAS_ALIAS | F_SF),
3537 CORE_INSN ("msub", 0x1b008000, 0x7fe08000, dp_3src, 0, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMER, F_HAS_ALIAS | F_SF),
3539 CORE_INSN ("smaddl",0x9b200000, 0xffe08000, dp_3src, 0, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS),
3541 CORE_INSN ("smsubl",0x9b208000, 0xffe08000, dp_3src, 0, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS),
3544 CORE_INSN ("umaddl",0x9ba00000, 0xffe08000, dp_3src, 0, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS),
3546 CORE_INSN ("umsubl",0x9ba08000, 0xffe08000, dp_3src, 0, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS),
5493 Y(INT_REG, regno, "Ra", 0, F(FLD_Ra), "an integer register") \
/netbsd-current/external/gpl3/binutils.old/dist/opcodes/
H A Dd30v-opc.c348 #define Ra (UNUSED + 1) macro
350 #define Ra2 (Ra + 1)
423 { SHORT_M, 0, { Ra, ATPAR, Rb, Rc } }, /* Ra,@(Rb,Rc) */
424 { SHORT_M, 1, { Ra, ATPAR, Rb, PLUS, Rc } }, /* Ra,@(Rb+,Rc) */
425 { SHORT_M, 2, { Ra, ATPAR, Rb, IMM6 } }, /* Ra,@(Rb,imm6) */
426 { SHORT_M, 3, { Ra, ATPAR, Rb, MINUS, Rc } }, /* Ra,
[all...]
H A Daarch64-tbl.h3521 CORE_INSN ("madd", 0x1b000000, 0x7fe08000, dp_3src, 0, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMER, F_HAS_ALIAS | F_SF),
3523 CORE_INSN ("msub", 0x1b008000, 0x7fe08000, dp_3src, 0, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMER, F_HAS_ALIAS | F_SF),
3525 CORE_INSN ("smaddl",0x9b200000, 0xffe08000, dp_3src, 0, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS),
3527 CORE_INSN ("smsubl",0x9b208000, 0xffe08000, dp_3src, 0, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS),
3530 CORE_INSN ("umaddl",0x9ba00000, 0xffe08000, dp_3src, 0, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS),
3532 CORE_INSN ("umsubl",0x9ba08000, 0xffe08000, dp_3src, 0, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEL, F_HAS_ALIAS),
5463 Y(INT_REG, regno, "Ra", 0, F(FLD_Ra), "an integer register") \
/netbsd-current/crypto/external/bsd/openssl.old/dist/crypto/ec/asm/
H A Decp_nistz256-x86_64.pl2556 my ($ONE,$INDEX,$Ra,$Rb,$Rc,$Rd,$Re,$Rf)=map("%xmm$_",(0..7));
2619 pxor $Ra, $Ra
2646 por $T0a, $Ra
2660 movdqu $Ra, 16*0($val)
2739 pxor $Ra, $Ra
2760 por $T0a, $Ra
2771 movdqu $Ra, 16*0($val)
2798 my ($TWO,$INDEX,$Ra,
[all...]
/netbsd-current/crypto/external/bsd/openssl/dist/crypto/ec/asm/
H A Decp_nistz256-x86_64.pl2558 my ($ONE,$INDEX,$Ra,$Rb,$Rc,$Rd,$Re,$Rf)=map("%xmm$_",(0..7));
2621 pxor $Ra, $Ra
2648 por $T0a, $Ra
2662 movdqu $Ra, 16*0($val)
2741 pxor $Ra, $Ra
2762 por $T0a, $Ra
2773 movdqu $Ra, 16*0($val)
2800 my ($TWO,$INDEX,$Ra,
[all...]
/netbsd-current/sys/arch/aarch64/aarch64/
H A Ddisasm.c2406 OP5FUNC(op_madd, sf, Rm, Ra, Rn, Rd)
2409 if (Ra == 31) {
2419 ZREGNAME(sf, Ra));
2423 OP5FUNC(op_msub, sf, Rm, Ra, Rn, Rd)
2426 if (Ra == 31) {
2436 ZREGNAME(sf, Ra));
2770 OP4FUNC(op_smaddl, Rm, Ra, Rn, Rd)
2773 if (Ra == 31) {
2783 ZREGNAME(1, Ra));
2792 OP4FUNC(op_smsubl, Rm, Ra, R
[all...]
/netbsd-current/external/gpl3/gdb.old/dist/sim/arm/
H A Dthumbemu.c1712 ARMword Ra = ntBITS (12, 15); local
1716 // SMLA<x><y><c> <Rd>,<Rn>,<Rm>,<Ra>
1722 tASSERT (Ra != 15);
1735 res += state->Reg[Ra];
1743 // MLS<c> <Rd>,<Rn>,<Rm>,<Ra>
1744 state->Reg[Rd] = state->Reg[Ra] - (state->Reg[Rn] * state->Reg[Rm]);
1750 if (Ra == 15)
1754 // MLA<c> <Rd>,<Rn>,<Rm>,<Ra>
1755 state->Reg[Rd] = state->Reg[Rn] * state->Reg[Rm] + state->Reg[Ra];
/netbsd-current/external/gpl3/gdb/dist/sim/arm/
H A Dthumbemu.c1715 ARMword Ra = ntBITS (12, 15); local
1719 // SMLA<x><y><c> <Rd>,<Rn>,<Rm>,<Ra>
1725 tASSERT (Ra != 15);
1738 res += state->Reg[Ra];
1746 // MLS<c> <Rd>,<Rn>,<Rm>,<Ra>
1747 state->Reg[Rd] = state->Reg[Ra] - (state->Reg[Rn] * state->Reg[Rm]);
1753 if (Ra == 15)
1757 // MLA<c> <Rd>,<Rn>,<Rm>,<Ra>
1758 state->Reg[Rd] = state->Reg[Rn] * state->Reg[Rm] + state->Reg[Ra];
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp2497 unsigned Ra = fieldFromInstruction(Insn, 12, 4); local
2509 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
/netbsd-current/external/gpl3/binutils/dist/gas/config/
H A Dtc-arm.c12985 unsigned Rd, Rn, Rm, Ra;
12990 Ra = inst.operands[3].reg;
12995 reject_bad_reg (Ra);
13000 inst.instruction |= Ra << 12;
12979 unsigned Rd, Rn, Rm, Ra; local
/netbsd-current/external/gpl3/gdb.old/dist/gas/config/
H A Dtc-arm.c12925 unsigned Rd, Rn, Rm, Ra;
12930 Ra = inst.operands[3].reg;
12935 reject_bad_reg (Ra);
12940 inst.instruction |= Ra << 12;
12919 unsigned Rd, Rn, Rm, Ra; local
/netbsd-current/external/gpl3/binutils.old/dist/gas/config/
H A Dtc-arm.c12985 unsigned Rd, Rn, Rm, Ra;
12990 Ra = inst.operands[3].reg;
12995 reject_bad_reg (Ra);
13000 inst.instruction |= Ra << 12;
12979 unsigned Rd, Rn, Rm, Ra; local

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