/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyReplacePhysRegs.cpp | 79 for (unsigned PReg = WebAssembly::NoRegister + 1; 80 PReg < WebAssembly::NUM_TARGET_REGS; ++PReg) { 82 if (PReg == WebAssembly::VALUE_STACK || PReg == WebAssembly::ARGUMENTS) 86 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(PReg); 88 for (auto I = MRI.reg_begin(PReg), E = MRI.reg_end(); I != E;) { 93 if (PReg == TRI.getFrameRegister(MF)) { 98 dbgs() << "replacing preg " << PReg << " with " << VReg << " ("
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
H A D | RegUsageInfoCollector.cpp | 155 for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) { 157 if (SavedRegs.test(PReg)) 161 if (!MRI->def_empty(PReg)) { 162 for (MCRegAliasIterator AI(PReg, TRI, true); AI.isValid(); ++AI) 170 if (UsedPhysRegsMask.test(PReg)) 171 SetRegAsDefined(PReg); 182 for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PReg [all...] |
H A D | RegisterUsageInfo.cpp | 95 for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) { 96 if (MachineOperand::clobbersPhysReg(&(FPRMPair->second[0]), PReg)) 97 OS << printReg(PReg, TRI) << " ";
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H A D | RegAllocPBQP.cpp | 627 MCRegister PReg(RawPRegOrder[I]); 628 if (MRI.isReserved(PReg)) 632 if (!RegMaskOverlaps.empty() && !RegMaskOverlaps.test(PReg)) 637 for (MCRegUnitIterator Units(PReg, &TRI); Units.isValid(); ++Units) { 647 VRegAllowed.push_back(PReg); 738 MCRegister PReg = G.getNodeMetadata(NId).getAllowedRegs()[AllocOpt - 1]; local 740 << TRI.getName(PReg) << "\n"); 741 assert(PReg != 0 && "Invalid preg selected."); 742 VRM.assignVirt2Phys(VReg, PReg); 764 Register PReg local [all...] |
H A D | CallingConvLower.cpp | 259 for (MCPhysReg PReg : RemainingRegs) { 260 Register VReg = MF.addLiveIn(PReg, RC); 261 Forwards.push_back(ForwardedRegister(VReg, PReg, RegVT));
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H A D | MachineRegisterInfo.cpp | 452 /// getLiveInVirtReg - If PReg is a live-in physical register, return the 454 Register MachineRegisterInfo::getLiveInVirtReg(MCRegister PReg) const { 456 if (LI.first == PReg)
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H A D | MachineFunction.cpp | 634 Register MachineFunction::addLiveIn(MCRegister PReg, argument 637 Register VReg = MRI.getLiveInVirtReg(PReg); 646 assert((VRegRC == RC || (VRegRC->contains(PReg) && 652 MRI.addLiveIn(PReg, VReg);
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H A D | MachineVerifier.cpp | 536 void MachineVerifier::report_context(MCPhysReg PReg) const { 537 errs() << "- p. register: " << printReg(PReg, TRI) << '\n';
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
H A D | HexagonBitTracker.h | 57 unsigned getNextPhysReg(unsigned PReg, unsigned Width) const; 58 unsigned getVirtRegFor(unsigned PReg) const;
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H A D | HexagonBitTracker.cpp | 1245 unsigned HexagonEvaluator::getNextPhysReg(unsigned PReg, unsigned Width) const { 1248 bool Is64 = DoubleRegsRegClass.contains(PReg); 1249 assert(PReg == 0 || Is64 || IntRegsRegClass.contains(PReg)); 1257 if (PReg == 0) 1265 if (Phys32[Idx32] == PReg) 1272 if (Phys64[Idx64] == PReg) 1284 unsigned HexagonEvaluator::getVirtRegFor(unsigned PReg) const { 1286 if (P.first == PReg)
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H A D | HexagonBlockRanges.cpp | 280 unsigned PReg = *RC.begin(); local 281 MCSubRegIndexIterator I(PReg, &TRI);
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H A D | HexagonInstrInfo.cpp | 1284 Register PReg = Op1.getReg(); local 1293 .addReg(PReg, S) 1302 .addReg(PReg, PState) 1317 Register PReg = Op1.getReg(); local 1328 .addReg(PReg, S) 1340 .addReg(PReg, PState)
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/netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
H A D | CallingConvLower.h | 168 ForwardedRegister(Register VReg, MCPhysReg PReg, MVT VT) argument 169 : VReg(VReg), PReg(PReg), VT(VT) {} 171 MCPhysReg PReg; member in struct:llvm::ForwardedRegister
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H A D | MachineRegisterInfo.h | 966 /// getLiveInVirtReg - If PReg is a live-in physical register, return the 968 Register getLiveInVirtReg(MCRegister PReg) const;
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H A D | MachineFunction.h | 735 Register addLiveIn(MCRegister PReg, const TargetRegisterClass *RC);
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
H A D | AArch64CallLowering.cpp | 503 MBB.addLiveIn(F.PReg); 504 MIRBuilder.buildCopy(Register(F.VReg), Register(F.PReg)); 998 Register ForwardedReg = F.PReg;
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
H A D | ARMLoadStoreOptimizer.cpp | 1015 Register PReg = PMO.getReg(); local 1017 : TRI->getEncodingValue(PReg); 1026 PReg == getLoadStoreBaseOp(*MI).getReg()) 1037 if (PReg == ARM::SP || PReg == ARM::PC)
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
H A D | X86FrameLowering.cpp | 3111 unsigned ScratchReg, SPReg, PReg, SPLimitOffset; 3116 PReg = X86::RBP; 3122 PReg = X86::EBP; 3137 .addReg(ScratchReg), PReg, false, SPLimitOffset); 3146 .addReg(ScratchReg), PReg, false, SPLimitOffset);
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H A D | X86ISelLowering.cpp | 4231 RegsToPass.push_back(std::make_pair(F.PReg, Val)); [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AsmParser/ |
H A D | AMDGPUAsmParser.cpp | 3225 auto PReg = mc2PseudoReg(Reg); local 3226 return isSGPR(PReg, TRI) && PReg != SGPR_NULL;
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 1245 addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC) argument 1248 MF.getRegInfo().addLiveIn(PReg, VReg);
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
H A D | M68kISelLowering.cpp | 650 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 5636 RegsToPass.emplace_back(F.PReg, Val);
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