Searched refs:PACKET3_SET_UCONFIG_REG_START (Results 1 - 10 of 10) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Dsoc15d.h277 #define PACKET3_SET_UCONFIG_REG_START 0x0000c000 macro
H A Dnvd.h290 #define PACKET3_SET_UCONFIG_REG_START 0x0000c000 macro
H A Dvid.h356 #define PACKET3_SET_UCONFIG_REG_START 0x0000c000 macro
H A Dcikd.h474 #define PACKET3_SET_UCONFIG_REG_START 0x0000c000 macro
H A Damdgpu_gfx_v10_0.c483 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
530 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
H A Damdgpu_gfx_v7_0.c2113 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
2380 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
H A Damdgpu_gfx_v9_0.c997 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
3167 (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START));
H A Damdgpu_gfx_v8_0.c862 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
/netbsd-current/sys/external/bsd/drm2/dist/drm/radeon/
H A Dcikd.h1940 #define PACKET3_SET_UCONFIG_REG_START 0x00030000 macro
H A Dradeon_cik.c3492 radeon_ring_write(ring, ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2));
3764 PACKET3_SET_UCONFIG_REG_START) >> 2));
3817 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2);

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