1/* $NetBSD: cikd.h,v 1.3 2021/12/18 23:44:58 riastradh Exp $ */ 2 3/* 4 * Copyright 2012 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Alex Deucher 25 */ 26#ifndef CIK_H 27#define CIK_H 28 29#define MC_SEQ_MISC0__MT__MASK 0xf0000000 30#define MC_SEQ_MISC0__MT__GDDR1 0x10000000 31#define MC_SEQ_MISC0__MT__DDR2 0x20000000 32#define MC_SEQ_MISC0__MT__GDDR3 0x30000000 33#define MC_SEQ_MISC0__MT__GDDR4 0x40000000 34#define MC_SEQ_MISC0__MT__GDDR5 0x50000000 35#define MC_SEQ_MISC0__MT__HBM 0x60000000 36#define MC_SEQ_MISC0__MT__DDR3 0xB0000000 37 38#define CP_ME_TABLE_SIZE 96 39 40/* display controller offsets used for crtc/cur/lut/grph/viewport/etc. */ 41#define CRTC0_REGISTER_OFFSET (0x1b7c - 0x1b7c) 42#define CRTC1_REGISTER_OFFSET (0x1e7c - 0x1b7c) 43#define CRTC2_REGISTER_OFFSET (0x417c - 0x1b7c) 44#define CRTC3_REGISTER_OFFSET (0x447c - 0x1b7c) 45#define CRTC4_REGISTER_OFFSET (0x477c - 0x1b7c) 46#define CRTC5_REGISTER_OFFSET (0x4a7c - 0x1b7c) 47 48/* hpd instance offsets */ 49#define HPD0_REGISTER_OFFSET (0x1807 - 0x1807) 50#define HPD1_REGISTER_OFFSET (0x180a - 0x1807) 51#define HPD2_REGISTER_OFFSET (0x180d - 0x1807) 52#define HPD3_REGISTER_OFFSET (0x1810 - 0x1807) 53#define HPD4_REGISTER_OFFSET (0x1813 - 0x1807) 54#define HPD5_REGISTER_OFFSET (0x1816 - 0x1807) 55 56#define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001 57#define HAWAII_GB_ADDR_CONFIG_GOLDEN 0x12011003 58 59#define AMDGPU_NUM_OF_VMIDS 8 60 61#define PIPEID(x) ((x) << 0) 62#define MEID(x) ((x) << 2) 63#define VMID(x) ((x) << 4) 64#define QUEUEID(x) ((x) << 8) 65 66#define mmCC_DRM_ID_STRAPS 0x1559 67#define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000 68 69#define mmCHUB_CONTROL 0x619 70#define BYPASS_VM (1 << 0) 71 72#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 73 74#define mmGRPH_LUT_10BIT_BYPASS_CONTROL 0x1a02 75#define LUT_10BIT_BYPASS_EN (1 << 8) 76 77# define CURSOR_MONO 0 78# define CURSOR_24_1 1 79# define CURSOR_24_8_PRE_MULT 2 80# define CURSOR_24_8_UNPRE_MULT 3 81# define CURSOR_URGENT_ALWAYS 0 82# define CURSOR_URGENT_1_8 1 83# define CURSOR_URGENT_1_4 2 84# define CURSOR_URGENT_3_8 3 85# define CURSOR_URGENT_1_2 4 86 87# define GRPH_DEPTH_8BPP 0 88# define GRPH_DEPTH_16BPP 1 89# define GRPH_DEPTH_32BPP 2 90/* 8 BPP */ 91# define GRPH_FORMAT_INDEXED 0 92/* 16 BPP */ 93# define GRPH_FORMAT_ARGB1555 0 94# define GRPH_FORMAT_ARGB565 1 95# define GRPH_FORMAT_ARGB4444 2 96# define GRPH_FORMAT_AI88 3 97# define GRPH_FORMAT_MONO16 4 98# define GRPH_FORMAT_BGRA5551 5 99/* 32 BPP */ 100# define GRPH_FORMAT_ARGB8888 0 101# define GRPH_FORMAT_ARGB2101010 1 102# define GRPH_FORMAT_32BPP_DIG 2 103# define GRPH_FORMAT_8B_ARGB2101010 3 104# define GRPH_FORMAT_BGRA1010102 4 105# define GRPH_FORMAT_8B_BGRA1010102 5 106# define GRPH_FORMAT_RGB111110 6 107# define GRPH_FORMAT_BGR101111 7 108# define ADDR_SURF_MACRO_TILE_ASPECT_1 0 109# define ADDR_SURF_MACRO_TILE_ASPECT_2 1 110# define ADDR_SURF_MACRO_TILE_ASPECT_4 2 111# define ADDR_SURF_MACRO_TILE_ASPECT_8 3 112# define GRPH_ARRAY_LINEAR_GENERAL 0 113# define GRPH_ARRAY_LINEAR_ALIGNED 1 114# define GRPH_ARRAY_1D_TILED_THIN1 2 115# define GRPH_ARRAY_2D_TILED_THIN1 4 116# define DISPLAY_MICRO_TILING 0 117# define THIN_MICRO_TILING 1 118# define DEPTH_MICRO_TILING 2 119# define ROTATED_MICRO_TILING 4 120# define GRPH_ENDIAN_NONE 0 121# define GRPH_ENDIAN_8IN16 1 122# define GRPH_ENDIAN_8IN32 2 123# define GRPH_ENDIAN_8IN64 3 124# define GRPH_RED_SEL_R 0 125# define GRPH_RED_SEL_G 1 126# define GRPH_RED_SEL_B 2 127# define GRPH_RED_SEL_A 3 128# define GRPH_GREEN_SEL_G 0 129# define GRPH_GREEN_SEL_B 1 130# define GRPH_GREEN_SEL_A 2 131# define GRPH_GREEN_SEL_R 3 132# define GRPH_BLUE_SEL_B 0 133# define GRPH_BLUE_SEL_A 1 134# define GRPH_BLUE_SEL_R 2 135# define GRPH_BLUE_SEL_G 3 136# define GRPH_ALPHA_SEL_A 0 137# define GRPH_ALPHA_SEL_R 1 138# define GRPH_ALPHA_SEL_G 2 139# define GRPH_ALPHA_SEL_B 3 140# define INPUT_GAMMA_USE_LUT 0 141# define INPUT_GAMMA_BYPASS 1 142# define INPUT_GAMMA_SRGB_24 2 143# define INPUT_GAMMA_XVYCC_222 3 144 145# define INPUT_CSC_BYPASS 0 146# define INPUT_CSC_PROG_COEFF 1 147# define INPUT_CSC_PROG_SHARED_MATRIXA 2 148 149# define OUTPUT_CSC_BYPASS 0 150# define OUTPUT_CSC_TV_RGB 1 151# define OUTPUT_CSC_YCBCR_601 2 152# define OUTPUT_CSC_YCBCR_709 3 153# define OUTPUT_CSC_PROG_COEFF 4 154# define OUTPUT_CSC_PROG_SHARED_MATRIXB 5 155 156# define DEGAMMA_BYPASS 0 157# define DEGAMMA_SRGB_24 1 158# define DEGAMMA_XVYCC_222 2 159# define GAMUT_REMAP_BYPASS 0 160# define GAMUT_REMAP_PROG_COEFF 1 161# define GAMUT_REMAP_PROG_SHARED_MATRIXA 2 162# define GAMUT_REMAP_PROG_SHARED_MATRIXB 3 163 164# define REGAMMA_BYPASS 0 165# define REGAMMA_SRGB_24 1 166# define REGAMMA_XVYCC_222 2 167# define REGAMMA_PROG_A 3 168# define REGAMMA_PROG_B 4 169 170# define FMT_CLAMP_6BPC 0 171# define FMT_CLAMP_8BPC 1 172# define FMT_CLAMP_10BPC 2 173 174# define HDMI_24BIT_DEEP_COLOR 0 175# define HDMI_30BIT_DEEP_COLOR 1 176# define HDMI_36BIT_DEEP_COLOR 2 177# define HDMI_ACR_HW 0 178# define HDMI_ACR_32 1 179# define HDMI_ACR_44 2 180# define HDMI_ACR_48 3 181# define HDMI_ACR_X1 1 182# define HDMI_ACR_X2 2 183# define HDMI_ACR_X4 4 184# define AFMT_AVI_INFO_Y_RGB 0 185# define AFMT_AVI_INFO_Y_YCBCR422 1 186# define AFMT_AVI_INFO_Y_YCBCR444 2 187 188#define NO_AUTO 0 189#define ES_AUTO 1 190#define GS_AUTO 2 191#define ES_AND_GS_AUTO 3 192 193# define ARRAY_MODE(x) ((x) << 2) 194# define PIPE_CONFIG(x) ((x) << 6) 195# define TILE_SPLIT(x) ((x) << 11) 196# define MICRO_TILE_MODE_NEW(x) ((x) << 22) 197# define SAMPLE_SPLIT(x) ((x) << 25) 198# define BANK_WIDTH(x) ((x) << 0) 199# define BANK_HEIGHT(x) ((x) << 2) 200# define MACRO_TILE_ASPECT(x) ((x) << 4) 201# define NUM_BANKS(x) ((x) << 6) 202 203#define MSG_ENTER_RLC_SAFE_MODE 1 204#define MSG_EXIT_RLC_SAFE_MODE 0 205 206/* 207 * PM4 208 */ 209#define PACKET_TYPE0 0 210#define PACKET_TYPE1 1 211#define PACKET_TYPE2 2 212#define PACKET_TYPE3 3 213 214#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 215#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 216#define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF) 217#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 218#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 219 ((reg) & 0xFFFF) | \ 220 ((n) & 0x3FFF) << 16) 221#define CP_PACKET2 0x80000000 222#define PACKET2_PAD_SHIFT 0 223#define PACKET2_PAD_MASK (0x3fffffff << 0) 224 225#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 226 227#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 228 (((op) & 0xFF) << 8) | \ 229 ((n) & 0x3FFF) << 16) 230 231#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) 232 233/* Packet 3 types */ 234#define PACKET3_NOP 0x10 235#define PACKET3_SET_BASE 0x11 236#define PACKET3_BASE_INDEX(x) ((x) << 0) 237#define CE_PARTITION_BASE 3 238#define PACKET3_CLEAR_STATE 0x12 239#define PACKET3_INDEX_BUFFER_SIZE 0x13 240#define PACKET3_DISPATCH_DIRECT 0x15 241#define PACKET3_DISPATCH_INDIRECT 0x16 242#define PACKET3_ATOMIC_GDS 0x1D 243#define PACKET3_ATOMIC_MEM 0x1E 244#define PACKET3_OCCLUSION_QUERY 0x1F 245#define PACKET3_SET_PREDICATION 0x20 246#define PACKET3_REG_RMW 0x21 247#define PACKET3_COND_EXEC 0x22 248#define PACKET3_PRED_EXEC 0x23 249#define PACKET3_DRAW_INDIRECT 0x24 250#define PACKET3_DRAW_INDEX_INDIRECT 0x25 251#define PACKET3_INDEX_BASE 0x26 252#define PACKET3_DRAW_INDEX_2 0x27 253#define PACKET3_CONTEXT_CONTROL 0x28 254#define PACKET3_INDEX_TYPE 0x2A 255#define PACKET3_DRAW_INDIRECT_MULTI 0x2C 256#define PACKET3_DRAW_INDEX_AUTO 0x2D 257#define PACKET3_NUM_INSTANCES 0x2F 258#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 259#define PACKET3_INDIRECT_BUFFER_CONST 0x33 260#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 261#define PACKET3_DRAW_INDEX_OFFSET_2 0x35 262#define PACKET3_DRAW_PREAMBLE 0x36 263#define PACKET3_WRITE_DATA 0x37 264#define WRITE_DATA_DST_SEL(x) ((x) << 8) 265 /* 0 - register 266 * 1 - memory (sync - via GRBM) 267 * 2 - gl2 268 * 3 - gds 269 * 4 - reserved 270 * 5 - memory (async - direct) 271 */ 272#define WR_ONE_ADDR (1 << 16) 273#define WR_CONFIRM (1 << 20) 274#define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) 275 /* 0 - LRU 276 * 1 - Stream 277 */ 278#define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) 279 /* 0 - me 280 * 1 - pfp 281 * 2 - ce 282 */ 283#define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 284#define PACKET3_MEM_SEMAPHORE 0x39 285# define PACKET3_SEM_USE_MAILBOX (0x1 << 16) 286# define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */ 287# define PACKET3_SEM_CLIENT_CODE ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */ 288# define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) 289# define PACKET3_SEM_SEL_WAIT (0x7 << 29) 290#define PACKET3_COPY_DW 0x3B 291#define PACKET3_WAIT_REG_MEM 0x3C 292#define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) 293 /* 0 - always 294 * 1 - < 295 * 2 - <= 296 * 3 - == 297 * 4 - != 298 * 5 - >= 299 * 6 - > 300 */ 301#define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) 302 /* 0 - reg 303 * 1 - mem 304 */ 305#define WAIT_REG_MEM_OPERATION(x) ((x) << 6) 306 /* 0 - wait_reg_mem 307 * 1 - wr_wait_wr_reg 308 */ 309#define WAIT_REG_MEM_ENGINE(x) ((x) << 8) 310 /* 0 - me 311 * 1 - pfp 312 */ 313#define PACKET3_INDIRECT_BUFFER 0x3F 314#define INDIRECT_BUFFER_TCL2_VOLATILE (1 << 22) 315#define INDIRECT_BUFFER_VALID (1 << 23) 316#define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28) 317 /* 0 - LRU 318 * 1 - Stream 319 * 2 - Bypass 320 */ 321#define PACKET3_COPY_DATA 0x40 322#define PACKET3_PFP_SYNC_ME 0x42 323#define PACKET3_SURFACE_SYNC 0x43 324# define PACKET3_DEST_BASE_0_ENA (1 << 0) 325# define PACKET3_DEST_BASE_1_ENA (1 << 1) 326# define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 327# define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 328# define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 329# define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 330# define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 331# define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 332# define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 333# define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 334# define PACKET3_DB_DEST_BASE_ENA (1 << 14) 335# define PACKET3_TCL1_VOL_ACTION_ENA (1 << 15) 336# define PACKET3_TC_VOL_ACTION_ENA (1 << 16) /* L2 */ 337# define PACKET3_TC_WB_ACTION_ENA (1 << 18) /* L2 */ 338# define PACKET3_DEST_BASE_2_ENA (1 << 19) 339# define PACKET3_DEST_BASE_3_ENA (1 << 21) 340# define PACKET3_TCL1_ACTION_ENA (1 << 22) 341# define PACKET3_TC_ACTION_ENA (1 << 23) /* L2 */ 342# define PACKET3_CB_ACTION_ENA (1 << 25) 343# define PACKET3_DB_ACTION_ENA (1 << 26) 344# define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) 345# define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28) 346# define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) 347#define PACKET3_COND_WRITE 0x45 348#define PACKET3_EVENT_WRITE 0x46 349#define EVENT_TYPE(x) ((x) << 0) 350#define EVENT_INDEX(x) ((x) << 8) 351 /* 0 - any non-TS event 352 * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_* 353 * 2 - SAMPLE_PIPELINESTAT 354 * 3 - SAMPLE_STREAMOUTSTAT* 355 * 4 - *S_PARTIAL_FLUSH 356 * 5 - EOP events 357 * 6 - EOS events 358 */ 359#define PACKET3_EVENT_WRITE_EOP 0x47 360#define EOP_TCL1_VOL_ACTION_EN (1 << 12) 361#define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */ 362#define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */ 363#define EOP_TCL1_ACTION_EN (1 << 16) 364#define EOP_TC_ACTION_EN (1 << 17) /* L2 */ 365#define EOP_TCL2_VOLATILE (1 << 24) 366#define EOP_CACHE_POLICY(x) ((x) << 25) 367 /* 0 - LRU 368 * 1 - Stream 369 * 2 - Bypass 370 */ 371#define DATA_SEL(x) ((x) << 29) 372 /* 0 - discard 373 * 1 - send low 32bit data 374 * 2 - send 64bit data 375 * 3 - send 64bit GPU counter value 376 * 4 - send 64bit sys counter value 377 */ 378#define INT_SEL(x) ((x) << 24) 379 /* 0 - none 380 * 1 - interrupt only (DATA_SEL = 0) 381 * 2 - interrupt when data write is confirmed 382 */ 383#define DST_SEL(x) ((x) << 16) 384 /* 0 - MC 385 * 1 - TC/L2 386 */ 387#define PACKET3_EVENT_WRITE_EOS 0x48 388#define PACKET3_RELEASE_MEM 0x49 389#define PACKET3_PREAMBLE_CNTL 0x4A 390# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 391# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 392#define PACKET3_DMA_DATA 0x50 393/* 1. header 394 * 2. CONTROL 395 * 3. SRC_ADDR_LO or DATA [31:0] 396 * 4. SRC_ADDR_HI [31:0] 397 * 5. DST_ADDR_LO [31:0] 398 * 6. DST_ADDR_HI [7:0] 399 * 7. COMMAND [30:21] | BYTE_COUNT [20:0] 400 */ 401/* CONTROL */ 402# define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0) 403 /* 0 - ME 404 * 1 - PFP 405 */ 406# define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13) 407 /* 0 - LRU 408 * 1 - Stream 409 * 2 - Bypass 410 */ 411# define PACKET3_DMA_DATA_SRC_VOLATILE (1 << 15) 412# define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20) 413 /* 0 - DST_ADDR using DAS 414 * 1 - GDS 415 * 3 - DST_ADDR using L2 416 */ 417# define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25) 418 /* 0 - LRU 419 * 1 - Stream 420 * 2 - Bypass 421 */ 422# define PACKET3_DMA_DATA_DST_VOLATILE (1 << 27) 423# define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29) 424 /* 0 - SRC_ADDR using SAS 425 * 1 - GDS 426 * 2 - DATA 427 * 3 - SRC_ADDR using L2 428 */ 429# define PACKET3_DMA_DATA_CP_SYNC (1 << 31) 430/* COMMAND */ 431# define PACKET3_DMA_DATA_DIS_WC (1 << 21) 432# define PACKET3_DMA_DATA_CMD_SRC_SWAP(x) ((x) << 22) 433 /* 0 - none 434 * 1 - 8 in 16 435 * 2 - 8 in 32 436 * 3 - 8 in 64 437 */ 438# define PACKET3_DMA_DATA_CMD_DST_SWAP(x) ((x) << 24) 439 /* 0 - none 440 * 1 - 8 in 16 441 * 2 - 8 in 32 442 * 3 - 8 in 64 443 */ 444# define PACKET3_DMA_DATA_CMD_SAS (1 << 26) 445 /* 0 - memory 446 * 1 - register 447 */ 448# define PACKET3_DMA_DATA_CMD_DAS (1 << 27) 449 /* 0 - memory 450 * 1 - register 451 */ 452# define PACKET3_DMA_DATA_CMD_SAIC (1 << 28) 453# define PACKET3_DMA_DATA_CMD_DAIC (1 << 29) 454# define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30) 455#define PACKET3_AQUIRE_MEM 0x58 456#define PACKET3_REWIND 0x59 457#define PACKET3_LOAD_UCONFIG_REG 0x5E 458#define PACKET3_LOAD_SH_REG 0x5F 459#define PACKET3_LOAD_CONFIG_REG 0x60 460#define PACKET3_LOAD_CONTEXT_REG 0x61 461#define PACKET3_SET_CONFIG_REG 0x68 462#define PACKET3_SET_CONFIG_REG_START 0x00002000 463#define PACKET3_SET_CONFIG_REG_END 0x00002c00 464#define PACKET3_SET_CONTEXT_REG 0x69 465#define PACKET3_SET_CONTEXT_REG_START 0x0000a000 466#define PACKET3_SET_CONTEXT_REG_END 0x0000a400 467#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 468#define PACKET3_SET_SH_REG 0x76 469#define PACKET3_SET_SH_REG_START 0x00002c00 470#define PACKET3_SET_SH_REG_END 0x00003000 471#define PACKET3_SET_SH_REG_OFFSET 0x77 472#define PACKET3_SET_QUEUE_REG 0x78 473#define PACKET3_SET_UCONFIG_REG 0x79 474#define PACKET3_SET_UCONFIG_REG_START 0x0000c000 475#define PACKET3_SET_UCONFIG_REG_END 0x0000c400 476#define PACKET3_SCRATCH_RAM_WRITE 0x7D 477#define PACKET3_SCRATCH_RAM_READ 0x7E 478#define PACKET3_LOAD_CONST_RAM 0x80 479#define PACKET3_WRITE_CONST_RAM 0x81 480#define PACKET3_DUMP_CONST_RAM 0x83 481#define PACKET3_INCREMENT_CE_COUNTER 0x84 482#define PACKET3_INCREMENT_DE_COUNTER 0x85 483#define PACKET3_WAIT_ON_CE_COUNTER 0x86 484#define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 485#define PACKET3_SWITCH_BUFFER 0x8B 486 487/* SDMA - first instance at 0xd000, second at 0xd800 */ 488#define SDMA0_REGISTER_OFFSET 0x0 /* not a register */ 489#define SDMA1_REGISTER_OFFSET 0x200 /* not a register */ 490#define SDMA_MAX_INSTANCE 2 491 492#define SDMA_PACKET(op, sub_op, e) ((((e) & 0xFFFF) << 16) | \ 493 (((sub_op) & 0xFF) << 8) | \ 494 (((op) & 0xFF) << 0)) 495/* sDMA opcodes */ 496#define SDMA_OPCODE_NOP 0 497# define SDMA_NOP_COUNT(x) (((x) & 0x3FFF) << 16) 498#define SDMA_OPCODE_COPY 1 499# define SDMA_COPY_SUB_OPCODE_LINEAR 0 500# define SDMA_COPY_SUB_OPCODE_TILED 1 501# define SDMA_COPY_SUB_OPCODE_SOA 3 502# define SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW 4 503# define SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW 5 504# define SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW 6 505#define SDMA_OPCODE_WRITE 2 506# define SDMA_WRITE_SUB_OPCODE_LINEAR 0 507# define SDMA_WRITE_SUB_OPCODE_TILED 1 508#define SDMA_OPCODE_INDIRECT_BUFFER 4 509#define SDMA_OPCODE_FENCE 5 510#define SDMA_OPCODE_TRAP 6 511#define SDMA_OPCODE_SEMAPHORE 7 512# define SDMA_SEMAPHORE_EXTRA_O (1 << 13) 513 /* 0 - increment 514 * 1 - write 1 515 */ 516# define SDMA_SEMAPHORE_EXTRA_S (1 << 14) 517 /* 0 - wait 518 * 1 - signal 519 */ 520# define SDMA_SEMAPHORE_EXTRA_M (1 << 15) 521 /* mailbox */ 522#define SDMA_OPCODE_POLL_REG_MEM 8 523# define SDMA_POLL_REG_MEM_EXTRA_OP(x) ((x) << 10) 524 /* 0 - wait_reg_mem 525 * 1 - wr_wait_wr_reg 526 */ 527# define SDMA_POLL_REG_MEM_EXTRA_FUNC(x) ((x) << 12) 528 /* 0 - always 529 * 1 - < 530 * 2 - <= 531 * 3 - == 532 * 4 - != 533 * 5 - >= 534 * 6 - > 535 */ 536# define SDMA_POLL_REG_MEM_EXTRA_M (1 << 15) 537 /* 0 = register 538 * 1 = memory 539 */ 540#define SDMA_OPCODE_COND_EXEC 9 541#define SDMA_OPCODE_CONSTANT_FILL 11 542# define SDMA_CONSTANT_FILL_EXTRA_SIZE(x) ((x) << 14) 543 /* 0 = byte fill 544 * 2 = DW fill 545 */ 546#define SDMA_OPCODE_GENERATE_PTE_PDE 12 547#define SDMA_OPCODE_TIMESTAMP 13 548# define SDMA_TIMESTAMP_SUB_OPCODE_SET_LOCAL 0 549# define SDMA_TIMESTAMP_SUB_OPCODE_GET_LOCAL 1 550# define SDMA_TIMESTAMP_SUB_OPCODE_GET_GLOBAL 2 551#define SDMA_OPCODE_SRBM_WRITE 14 552# define SDMA_SRBM_WRITE_EXTRA_BYTE_ENABLE(x) ((x) << 12) 553 /* byte mask */ 554 555#define VCE_CMD_NO_OP 0x00000000 556#define VCE_CMD_END 0x00000001 557#define VCE_CMD_IB 0x00000002 558#define VCE_CMD_FENCE 0x00000003 559#define VCE_CMD_TRAP 0x00000004 560#define VCE_CMD_IB_AUTO 0x00000005 561#define VCE_CMD_SEMAPHORE 0x00000006 562 563/* if PTR32, these are the bases for scratch and lds */ 564#define PRIVATE_BASE(x) ((x) << 0) /* scratch */ 565#define SHARED_BASE(x) ((x) << 16) /* LDS */ 566 567#define KFD_CIK_SDMA_QUEUE_OFFSET (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL) 568 569/* valid for both DEFAULT_MTYPE and APE1_MTYPE */ 570enum { 571 MTYPE_CACHED = 0, 572 MTYPE_NONCACHED = 3 573}; 574 575/* mmPA_SC_RASTER_CONFIG mask */ 576#define RB_MAP_PKR0(x) ((x) << 0) 577#define RB_MAP_PKR0_MASK (0x3 << 0) 578#define RB_MAP_PKR1(x) ((x) << 2) 579#define RB_MAP_PKR1_MASK (0x3 << 2) 580#define RB_XSEL2(x) ((x) << 4) 581#define RB_XSEL2_MASK (0x3 << 4) 582#define RB_XSEL (1 << 6) 583#define RB_YSEL (1 << 7) 584#define PKR_MAP(x) ((x) << 8) 585#define PKR_MAP_MASK (0x3 << 8) 586#define PKR_XSEL(x) ((x) << 10) 587#define PKR_XSEL_MASK (0x3 << 10) 588#define PKR_YSEL(x) ((x) << 12) 589#define PKR_YSEL_MASK (0x3 << 12) 590#define SC_MAP(x) ((x) << 16) 591#define SC_MAP_MASK (0x3 << 16) 592#define SC_XSEL(x) ((x) << 18) 593#define SC_XSEL_MASK (0x3 << 18) 594#define SC_YSEL(x) ((x) << 20) 595#define SC_YSEL_MASK (0x3 << 20) 596#define SE_MAP(x) ((x) << 24) 597#define SE_MAP_MASK (0x3 << 24) 598#define SE_XSEL(x) ((x) << 26) 599#define SE_XSEL_MASK (0x3 << 26) 600#define SE_YSEL(x) ((x) << 28) 601#define SE_YSEL_MASK (0x3 << 28) 602 603/* mmPA_SC_RASTER_CONFIG_1 mask */ 604#define SE_PAIR_MAP(x) ((x) << 0) 605#define SE_PAIR_MAP_MASK (0x3 << 0) 606#define SE_PAIR_XSEL(x) ((x) << 2) 607#define SE_PAIR_XSEL_MASK (0x3 << 2) 608#define SE_PAIR_YSEL(x) ((x) << 4) 609#define SE_PAIR_YSEL_MASK (0x3 << 4) 610 611#endif 612