Searched refs:NBIO_BASE (Results 1 - 10 of 10) sorted by relevance
| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | amdgpu_navi10_reg_init.c | 43 adev->reg_offset[NBIO_HWIP][i] = (const uint32_t *)(&(NBIO_BASE.instance[i]));
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| H A D | amdgpu_vega20_reg_init.c | 43 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
54 adev->reg_offset[NBIF_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
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| H A D | amdgpu_vega10_reg_init.c | 43 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/ |
| H A D | amdgpu_dce120_resource.c | 135 #define NBIO_BASE(seg) \ macro
493 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3 + NBIO_BASE(mmBIOS_SCRATCH_3_BASE_IDX),
494 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 + NBIO_BASE(mmBIOS_SCRATCH_6_BASE_IDX)
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/ |
| H A D | navi10_ip_offset.h | 99 static const struct IP_BASE NBIO_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0, 0 } }, variable in typeref:struct:IP_BASE
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| H A D | vega20_ip_offset.h | 101 static const struct IP_BASE NBIO_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0, 0 } }, variable in typeref:struct:IP_BASE
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| H A D | vega10_ip_offset.h | 45 static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } }, variable in typeref:struct:IP_BASE
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| H A D | amdgpu_dcn10_resource.c | 193 #define NBIO_BASE(seg) \ macro
197 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
| H A D | amdgpu_dcn21_resource.c | 318 #define NBIO_BASE(seg) \ macro
322 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| H A D | amdgpu_dcn20_resource.c | 407 #define NBIO_BASE(seg) \ macro
411 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
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