1/* $NetBSD: vega20_ip_offset.h,v 1.2 2021/12/18 23:45:08 riastradh Exp $ */ 2 3/* 4 * Copyright (C) 2018 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23#ifndef _vega20_ip_offset_HEADER 24#define _vega20_ip_offset_HEADER 25 26#define MAX_INSTANCE 6 27#define MAX_SEGMENT 6 28 29 30struct IP_BASE_INSTANCE 31{ 32 unsigned int segment[MAX_SEGMENT]; 33}; 34 35struct IP_BASE 36{ 37 struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; 38}; 39 40 41static const struct IP_BASE ATHUB_BASE ={ { { { 0x00000C20, 0, 0, 0, 0, 0 } }, 42 { { 0, 0, 0, 0, 0, 0 } }, 43 { { 0, 0, 0, 0, 0, 0 } }, 44 { { 0, 0, 0, 0, 0, 0 } }, 45 { { 0, 0, 0, 0, 0, 0 } }, 46 { { 0, 0, 0, 0, 0, 0 } } } }; 47static const struct IP_BASE CLK_BASE ={ { { { 0x00016C00, 0x00016E00, 0x00017000, 0x00017200, 0x0001B000, 0x0001B200 } }, 48 { { 0, 0, 0, 0, 0, 0 } }, 49 { { 0, 0, 0, 0, 0, 0 } }, 50 { { 0, 0, 0, 0, 0, 0 } }, 51 { { 0, 0, 0, 0, 0, 0 } }, 52 { { 0, 0, 0, 0, 0, 0 } } } }; 53static const struct IP_BASE DCE_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0, 0 } }, 54 { { 0, 0, 0, 0, 0, 0 } }, 55 { { 0, 0, 0, 0, 0, 0 } }, 56 { { 0, 0, 0, 0, 0, 0 } }, 57 { { 0, 0, 0, 0, 0, 0 } }, 58 { { 0, 0, 0, 0, 0, 0 } } } }; 59static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0, 0, 0, 0, 0 } }, 60 { { 0, 0, 0, 0, 0, 0 } }, 61 { { 0, 0, 0, 0, 0, 0 } }, 62 { { 0, 0, 0, 0, 0, 0 } }, 63 { { 0, 0, 0, 0, 0, 0 } }, 64 { { 0, 0, 0, 0, 0, 0 } } } }; 65static const struct IP_BASE FUSE_BASE ={ { { { 0x00017400, 0, 0, 0, 0, 0 } }, 66 { { 0, 0, 0, 0, 0, 0 } }, 67 { { 0, 0, 0, 0, 0, 0 } }, 68 { { 0, 0, 0, 0, 0, 0 } }, 69 { { 0, 0, 0, 0, 0, 0 } }, 70 { { 0, 0, 0, 0, 0, 0 } } } }; 71static const struct IP_BASE GC_BASE ={ { { { 0x00002000, 0x0000A000, 0, 0, 0, 0 } }, 72 { { 0, 0, 0, 0, 0, 0 } }, 73 { { 0, 0, 0, 0, 0, 0 } }, 74 { { 0, 0, 0, 0, 0, 0 } }, 75 { { 0, 0, 0, 0, 0, 0 } }, 76 { { 0, 0, 0, 0, 0, 0 } } } }; 77static const struct IP_BASE HDP_BASE ={ { { { 0x00000F20, 0, 0, 0, 0, 0 } }, 78 { { 0, 0, 0, 0, 0, 0 } }, 79 { { 0, 0, 0, 0, 0, 0 } }, 80 { { 0, 0, 0, 0, 0, 0 } }, 81 { { 0, 0, 0, 0, 0, 0 } }, 82 { { 0, 0, 0, 0, 0, 0 } } } }; 83static const struct IP_BASE MMHUB_BASE ={ { { { 0x0001A000, 0, 0, 0, 0, 0 } }, 84 { { 0, 0, 0, 0, 0, 0 } }, 85 { { 0, 0, 0, 0, 0, 0 } }, 86 { { 0, 0, 0, 0, 0, 0 } }, 87 { { 0, 0, 0, 0, 0, 0 } }, 88 { { 0, 0, 0, 0, 0, 0 } } } }; 89static const struct IP_BASE MP0_BASE ={ { { { 0x00016000, 0, 0, 0, 0, 0 } }, 90 { { 0, 0, 0, 0, 0, 0 } }, 91 { { 0, 0, 0, 0, 0, 0 } }, 92 { { 0, 0, 0, 0, 0, 0 } }, 93 { { 0, 0, 0, 0, 0, 0 } }, 94 { { 0, 0, 0, 0, 0, 0 } } } }; 95static const struct IP_BASE MP1_BASE ={ { { { 0x00016000, 0, 0, 0, 0, 0 } }, 96 { { 0, 0, 0, 0, 0, 0 } }, 97 { { 0, 0, 0, 0, 0, 0 } }, 98 { { 0, 0, 0, 0, 0, 0 } }, 99 { { 0, 0, 0, 0, 0, 0 } }, 100 { { 0, 0, 0, 0, 0, 0 } } } }; 101static const struct IP_BASE NBIO_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0, 0 } }, 102 { { 0, 0, 0, 0, 0, 0 } }, 103 { { 0, 0, 0, 0, 0, 0 } }, 104 { { 0, 0, 0, 0, 0, 0 } }, 105 { { 0, 0, 0, 0, 0, 0 } }, 106 { { 0, 0, 0, 0, 0, 0 } } } }; 107static const struct IP_BASE OSSSYS_BASE ={ { { { 0x000010A0, 0, 0, 0, 0, 0 } }, 108 { { 0, 0, 0, 0, 0, 0 } }, 109 { { 0, 0, 0, 0, 0, 0 } }, 110 { { 0, 0, 0, 0, 0, 0 } }, 111 { { 0, 0, 0, 0, 0, 0 } }, 112 { { 0, 0, 0, 0, 0, 0 } } } }; 113static const struct IP_BASE SDMA0_BASE ={ { { { 0x00001260, 0, 0, 0, 0, 0 } }, 114 { { 0, 0, 0, 0, 0, 0 } }, 115 { { 0, 0, 0, 0, 0, 0 } }, 116 { { 0, 0, 0, 0, 0, 0 } }, 117 { { 0, 0, 0, 0, 0, 0 } }, 118 { { 0, 0, 0, 0, 0, 0 } } } }; 119static const struct IP_BASE SDMA1_BASE ={ { { { 0x00001860, 0, 0, 0, 0, 0 } }, 120 { { 0, 0, 0, 0, 0, 0 } }, 121 { { 0, 0, 0, 0, 0, 0 } }, 122 { { 0, 0, 0, 0, 0, 0 } }, 123 { { 0, 0, 0, 0, 0, 0 } }, 124 { { 0, 0, 0, 0, 0, 0 } } } }; 125static const struct IP_BASE SMUIO_BASE ={ { { { 0x00016800, 0x00016A00, 0, 0, 0, 0 } }, 126 { { 0, 0, 0, 0, 0, 0 } }, 127 { { 0, 0, 0, 0, 0, 0 } }, 128 { { 0, 0, 0, 0, 0, 0 } }, 129 { { 0, 0, 0, 0, 0, 0 } }, 130 { { 0, 0, 0, 0, 0, 0 } } } }; 131static const struct IP_BASE THM_BASE ={ { { { 0x00016600, 0, 0, 0, 0, 0 } }, 132 { { 0, 0, 0, 0, 0, 0 } }, 133 { { 0, 0, 0, 0, 0, 0 } }, 134 { { 0, 0, 0, 0, 0, 0 } }, 135 { { 0, 0, 0, 0, 0, 0 } }, 136 { { 0, 0, 0, 0, 0, 0 } } } }; 137static const struct IP_BASE UMC_BASE ={ { { { 0x00014000, 0, 0, 0, 0, 0 } }, 138 { { 0, 0, 0, 0, 0, 0 } }, 139 { { 0, 0, 0, 0, 0, 0 } }, 140 { { 0, 0, 0, 0, 0, 0 } }, 141 { { 0, 0, 0, 0, 0, 0 } }, 142 { { 0, 0, 0, 0, 0, 0 } } } }; 143static const struct IP_BASE UVD_BASE ={ { { { 0x00007800, 0x00007E00, 0, 0, 0, 0 } }, 144 { { 0, 0x00009000, 0, 0, 0, 0 } }, 145 { { 0, 0, 0, 0, 0, 0 } }, 146 { { 0, 0, 0, 0, 0, 0 } }, 147 { { 0, 0, 0, 0, 0, 0 } }, 148 { { 0, 0, 0, 0, 0, 0 } } } }; 149/* Adjust VCE_BASE to make vce_4_1 use vce_4_0 offset header files*/ 150static const struct IP_BASE VCE_BASE ={ { { { 0x00007E00/* 0x00008800 */, 0, 0, 0, 0, 0 } }, 151 { { 0, 0, 0, 0, 0, 0 } }, 152 { { 0, 0, 0, 0, 0, 0 } }, 153 { { 0, 0, 0, 0, 0, 0 } }, 154 { { 0, 0, 0, 0, 0, 0 } }, 155 { { 0, 0, 0, 0, 0, 0 } } } }; 156static const struct IP_BASE XDMA_BASE ={ { { { 0x00003400, 0, 0, 0, 0, 0 } }, 157 { { 0, 0, 0, 0, 0, 0 } }, 158 { { 0, 0, 0, 0, 0, 0 } }, 159 { { 0, 0, 0, 0, 0, 0 } }, 160 { { 0, 0, 0, 0, 0, 0 } }, 161 { { 0, 0, 0, 0, 0, 0 } } } }; 162static const struct IP_BASE RSMU_BASE ={ { { { 0x00012000, 0, 0, 0, 0, 0 } }, 163 { { 0, 0, 0, 0, 0, 0 } }, 164 { { 0, 0, 0, 0, 0, 0 } }, 165 { { 0, 0, 0, 0, 0, 0 } }, 166 { { 0, 0, 0, 0, 0, 0 } }, 167 { { 0, 0, 0, 0, 0, 0 } } } }; 168 169 170#define ATHUB_BASE__INST0_SEG0 0x00000C20 171#define ATHUB_BASE__INST0_SEG1 0 172#define ATHUB_BASE__INST0_SEG2 0 173#define ATHUB_BASE__INST0_SEG3 0 174#define ATHUB_BASE__INST0_SEG4 0 175#define ATHUB_BASE__INST0_SEG5 0 176 177#define ATHUB_BASE__INST1_SEG0 0 178#define ATHUB_BASE__INST1_SEG1 0 179#define ATHUB_BASE__INST1_SEG2 0 180#define ATHUB_BASE__INST1_SEG3 0 181#define ATHUB_BASE__INST1_SEG4 0 182#define ATHUB_BASE__INST1_SEG5 0 183 184#define ATHUB_BASE__INST2_SEG0 0 185#define ATHUB_BASE__INST2_SEG1 0 186#define ATHUB_BASE__INST2_SEG2 0 187#define ATHUB_BASE__INST2_SEG3 0 188#define ATHUB_BASE__INST2_SEG4 0 189#define ATHUB_BASE__INST2_SEG5 0 190 191#define ATHUB_BASE__INST3_SEG0 0 192#define ATHUB_BASE__INST3_SEG1 0 193#define ATHUB_BASE__INST3_SEG2 0 194#define ATHUB_BASE__INST3_SEG3 0 195#define ATHUB_BASE__INST3_SEG4 0 196#define ATHUB_BASE__INST3_SEG5 0 197 198#define ATHUB_BASE__INST4_SEG0 0 199#define ATHUB_BASE__INST4_SEG1 0 200#define ATHUB_BASE__INST4_SEG2 0 201#define ATHUB_BASE__INST4_SEG3 0 202#define ATHUB_BASE__INST4_SEG4 0 203#define ATHUB_BASE__INST4_SEG5 0 204 205#define ATHUB_BASE__INST5_SEG0 0 206#define ATHUB_BASE__INST5_SEG1 0 207#define ATHUB_BASE__INST5_SEG2 0 208#define ATHUB_BASE__INST5_SEG3 0 209#define ATHUB_BASE__INST5_SEG4 0 210#define ATHUB_BASE__INST5_SEG5 0 211 212#define CLK_BASE__INST0_SEG0 0x00016C00 213#define CLK_BASE__INST0_SEG1 0x00016E00 214#define CLK_BASE__INST0_SEG2 0x00017000 215#define CLK_BASE__INST0_SEG3 0x00017200 216#define CLK_BASE__INST0_SEG4 0x0001B000 217#define CLK_BASE__INST0_SEG5 0x0001B200 218 219#define CLK_BASE__INST1_SEG0 0 220#define CLK_BASE__INST1_SEG1 0 221#define CLK_BASE__INST1_SEG2 0 222#define CLK_BASE__INST1_SEG3 0 223#define CLK_BASE__INST1_SEG4 0 224#define CLK_BASE__INST1_SEG5 0 225 226#define CLK_BASE__INST2_SEG0 0 227#define CLK_BASE__INST2_SEG1 0 228#define CLK_BASE__INST2_SEG2 0 229#define CLK_BASE__INST2_SEG3 0 230#define CLK_BASE__INST2_SEG4 0 231#define CLK_BASE__INST2_SEG5 0 232 233#define CLK_BASE__INST3_SEG0 0 234#define CLK_BASE__INST3_SEG1 0 235#define CLK_BASE__INST3_SEG2 0 236#define CLK_BASE__INST3_SEG3 0 237#define CLK_BASE__INST3_SEG4 0 238#define CLK_BASE__INST3_SEG5 0 239 240#define CLK_BASE__INST4_SEG0 0 241#define CLK_BASE__INST4_SEG1 0 242#define CLK_BASE__INST4_SEG2 0 243#define CLK_BASE__INST4_SEG3 0 244#define CLK_BASE__INST4_SEG4 0 245#define CLK_BASE__INST4_SEG5 0 246 247#define CLK_BASE__INST5_SEG0 0 248#define CLK_BASE__INST5_SEG1 0 249#define CLK_BASE__INST5_SEG2 0 250#define CLK_BASE__INST5_SEG3 0 251#define CLK_BASE__INST5_SEG4 0 252#define CLK_BASE__INST5_SEG5 0 253 254#define DCE_BASE__INST0_SEG0 0x00000012 255#define DCE_BASE__INST0_SEG1 0x000000C0 256#define DCE_BASE__INST0_SEG2 0x000034C0 257#define DCE_BASE__INST0_SEG3 0 258#define DCE_BASE__INST0_SEG4 0 259#define DCE_BASE__INST0_SEG5 0 260 261#define DCE_BASE__INST1_SEG0 0 262#define DCE_BASE__INST1_SEG1 0 263#define DCE_BASE__INST1_SEG2 0 264#define DCE_BASE__INST1_SEG3 0 265#define DCE_BASE__INST1_SEG4 0 266#define DCE_BASE__INST1_SEG5 0 267 268#define DCE_BASE__INST2_SEG0 0 269#define DCE_BASE__INST2_SEG1 0 270#define DCE_BASE__INST2_SEG2 0 271#define DCE_BASE__INST2_SEG3 0 272#define DCE_BASE__INST2_SEG4 0 273#define DCE_BASE__INST2_SEG5 0 274 275#define DCE_BASE__INST3_SEG0 0 276#define DCE_BASE__INST3_SEG1 0 277#define DCE_BASE__INST3_SEG2 0 278#define DCE_BASE__INST3_SEG3 0 279#define DCE_BASE__INST3_SEG4 0 280#define DCE_BASE__INST3_SEG5 0 281 282#define DCE_BASE__INST4_SEG0 0 283#define DCE_BASE__INST4_SEG1 0 284#define DCE_BASE__INST4_SEG2 0 285#define DCE_BASE__INST4_SEG3 0 286#define DCE_BASE__INST4_SEG4 0 287#define DCE_BASE__INST4_SEG5 0 288 289#define DCE_BASE__INST5_SEG0 0 290#define DCE_BASE__INST5_SEG1 0 291#define DCE_BASE__INST5_SEG2 0 292#define DCE_BASE__INST5_SEG3 0 293#define DCE_BASE__INST5_SEG4 0 294#define DCE_BASE__INST5_SEG5 0 295 296#define DF_BASE__INST0_SEG0 0x00007000 297#define DF_BASE__INST0_SEG1 0 298#define DF_BASE__INST0_SEG2 0 299#define DF_BASE__INST0_SEG3 0 300#define DF_BASE__INST0_SEG4 0 301#define DF_BASE__INST0_SEG5 0 302 303#define DF_BASE__INST1_SEG0 0 304#define DF_BASE__INST1_SEG1 0 305#define DF_BASE__INST1_SEG2 0 306#define DF_BASE__INST1_SEG3 0 307#define DF_BASE__INST1_SEG4 0 308#define DF_BASE__INST1_SEG5 0 309 310#define DF_BASE__INST2_SEG0 0 311#define DF_BASE__INST2_SEG1 0 312#define DF_BASE__INST2_SEG2 0 313#define DF_BASE__INST2_SEG3 0 314#define DF_BASE__INST2_SEG4 0 315#define DF_BASE__INST2_SEG5 0 316 317#define DF_BASE__INST3_SEG0 0 318#define DF_BASE__INST3_SEG1 0 319#define DF_BASE__INST3_SEG2 0 320#define DF_BASE__INST3_SEG3 0 321#define DF_BASE__INST3_SEG4 0 322#define DF_BASE__INST3_SEG5 0 323 324#define DF_BASE__INST4_SEG0 0 325#define DF_BASE__INST4_SEG1 0 326#define DF_BASE__INST4_SEG2 0 327#define DF_BASE__INST4_SEG3 0 328#define DF_BASE__INST4_SEG4 0 329#define DF_BASE__INST4_SEG5 0 330 331#define DF_BASE__INST5_SEG0 0 332#define DF_BASE__INST5_SEG1 0 333#define DF_BASE__INST5_SEG2 0 334#define DF_BASE__INST5_SEG3 0 335#define DF_BASE__INST5_SEG4 0 336#define DF_BASE__INST5_SEG5 0 337 338#define FUSE_BASE__INST0_SEG0 0x00017400 339#define FUSE_BASE__INST0_SEG1 0 340#define FUSE_BASE__INST0_SEG2 0 341#define FUSE_BASE__INST0_SEG3 0 342#define FUSE_BASE__INST0_SEG4 0 343#define FUSE_BASE__INST0_SEG5 0 344 345#define FUSE_BASE__INST1_SEG0 0 346#define FUSE_BASE__INST1_SEG1 0 347#define FUSE_BASE__INST1_SEG2 0 348#define FUSE_BASE__INST1_SEG3 0 349#define FUSE_BASE__INST1_SEG4 0 350#define FUSE_BASE__INST1_SEG5 0 351 352#define FUSE_BASE__INST2_SEG0 0 353#define FUSE_BASE__INST2_SEG1 0 354#define FUSE_BASE__INST2_SEG2 0 355#define FUSE_BASE__INST2_SEG3 0 356#define FUSE_BASE__INST2_SEG4 0 357#define FUSE_BASE__INST2_SEG5 0 358 359#define FUSE_BASE__INST3_SEG0 0 360#define FUSE_BASE__INST3_SEG1 0 361#define FUSE_BASE__INST3_SEG2 0 362#define FUSE_BASE__INST3_SEG3 0 363#define FUSE_BASE__INST3_SEG4 0 364#define FUSE_BASE__INST3_SEG5 0 365 366#define FUSE_BASE__INST4_SEG0 0 367#define FUSE_BASE__INST4_SEG1 0 368#define FUSE_BASE__INST4_SEG2 0 369#define FUSE_BASE__INST4_SEG3 0 370#define FUSE_BASE__INST4_SEG4 0 371#define FUSE_BASE__INST4_SEG5 0 372 373#define FUSE_BASE__INST5_SEG0 0 374#define FUSE_BASE__INST5_SEG1 0 375#define FUSE_BASE__INST5_SEG2 0 376#define FUSE_BASE__INST5_SEG3 0 377#define FUSE_BASE__INST5_SEG4 0 378#define FUSE_BASE__INST5_SEG5 0 379 380#define GC_BASE__INST0_SEG0 0x00002000 381#define GC_BASE__INST0_SEG1 0x0000A000 382#define GC_BASE__INST0_SEG2 0 383#define GC_BASE__INST0_SEG3 0 384#define GC_BASE__INST0_SEG4 0 385#define GC_BASE__INST0_SEG5 0 386 387#define GC_BASE__INST1_SEG0 0 388#define GC_BASE__INST1_SEG1 0 389#define GC_BASE__INST1_SEG2 0 390#define GC_BASE__INST1_SEG3 0 391#define GC_BASE__INST1_SEG4 0 392#define GC_BASE__INST1_SEG5 0 393 394#define GC_BASE__INST2_SEG0 0 395#define GC_BASE__INST2_SEG1 0 396#define GC_BASE__INST2_SEG2 0 397#define GC_BASE__INST2_SEG3 0 398#define GC_BASE__INST2_SEG4 0 399#define GC_BASE__INST2_SEG5 0 400 401#define GC_BASE__INST3_SEG0 0 402#define GC_BASE__INST3_SEG1 0 403#define GC_BASE__INST3_SEG2 0 404#define GC_BASE__INST3_SEG3 0 405#define GC_BASE__INST3_SEG4 0 406#define GC_BASE__INST3_SEG5 0 407 408#define GC_BASE__INST4_SEG0 0 409#define GC_BASE__INST4_SEG1 0 410#define GC_BASE__INST4_SEG2 0 411#define GC_BASE__INST4_SEG3 0 412#define GC_BASE__INST4_SEG4 0 413#define GC_BASE__INST4_SEG5 0 414 415#define GC_BASE__INST5_SEG0 0 416#define GC_BASE__INST5_SEG1 0 417#define GC_BASE__INST5_SEG2 0 418#define GC_BASE__INST5_SEG3 0 419#define GC_BASE__INST5_SEG4 0 420#define GC_BASE__INST5_SEG5 0 421 422#define HDP_BASE__INST0_SEG0 0x00000F20 423#define HDP_BASE__INST0_SEG1 0 424#define HDP_BASE__INST0_SEG2 0 425#define HDP_BASE__INST0_SEG3 0 426#define HDP_BASE__INST0_SEG4 0 427#define HDP_BASE__INST0_SEG5 0 428 429#define HDP_BASE__INST1_SEG0 0 430#define HDP_BASE__INST1_SEG1 0 431#define HDP_BASE__INST1_SEG2 0 432#define HDP_BASE__INST1_SEG3 0 433#define HDP_BASE__INST1_SEG4 0 434#define HDP_BASE__INST1_SEG5 0 435 436#define HDP_BASE__INST2_SEG0 0 437#define HDP_BASE__INST2_SEG1 0 438#define HDP_BASE__INST2_SEG2 0 439#define HDP_BASE__INST2_SEG3 0 440#define HDP_BASE__INST2_SEG4 0 441#define HDP_BASE__INST2_SEG5 0 442 443#define HDP_BASE__INST3_SEG0 0 444#define HDP_BASE__INST3_SEG1 0 445#define HDP_BASE__INST3_SEG2 0 446#define HDP_BASE__INST3_SEG3 0 447#define HDP_BASE__INST3_SEG4 0 448#define HDP_BASE__INST3_SEG5 0 449 450#define HDP_BASE__INST4_SEG0 0 451#define HDP_BASE__INST4_SEG1 0 452#define HDP_BASE__INST4_SEG2 0 453#define HDP_BASE__INST4_SEG3 0 454#define HDP_BASE__INST4_SEG4 0 455#define HDP_BASE__INST4_SEG5 0 456 457#define HDP_BASE__INST5_SEG0 0 458#define HDP_BASE__INST5_SEG1 0 459#define HDP_BASE__INST5_SEG2 0 460#define HDP_BASE__INST5_SEG3 0 461#define HDP_BASE__INST5_SEG4 0 462#define HDP_BASE__INST5_SEG5 0 463 464#define MMHUB_BASE__INST0_SEG0 0x0001A000 465#define MMHUB_BASE__INST0_SEG1 0 466#define MMHUB_BASE__INST0_SEG2 0 467#define MMHUB_BASE__INST0_SEG3 0 468#define MMHUB_BASE__INST0_SEG4 0 469#define MMHUB_BASE__INST0_SEG5 0 470 471#define MMHUB_BASE__INST1_SEG0 0 472#define MMHUB_BASE__INST1_SEG1 0 473#define MMHUB_BASE__INST1_SEG2 0 474#define MMHUB_BASE__INST1_SEG3 0 475#define MMHUB_BASE__INST1_SEG4 0 476#define MMHUB_BASE__INST1_SEG5 0 477 478#define MMHUB_BASE__INST2_SEG0 0 479#define MMHUB_BASE__INST2_SEG1 0 480#define MMHUB_BASE__INST2_SEG2 0 481#define MMHUB_BASE__INST2_SEG3 0 482#define MMHUB_BASE__INST2_SEG4 0 483#define MMHUB_BASE__INST2_SEG5 0 484 485#define MMHUB_BASE__INST3_SEG0 0 486#define MMHUB_BASE__INST3_SEG1 0 487#define MMHUB_BASE__INST3_SEG2 0 488#define MMHUB_BASE__INST3_SEG3 0 489#define MMHUB_BASE__INST3_SEG4 0 490#define MMHUB_BASE__INST3_SEG5 0 491 492#define MMHUB_BASE__INST4_SEG0 0 493#define MMHUB_BASE__INST4_SEG1 0 494#define MMHUB_BASE__INST4_SEG2 0 495#define MMHUB_BASE__INST4_SEG3 0 496#define MMHUB_BASE__INST4_SEG4 0 497#define MMHUB_BASE__INST4_SEG5 0 498 499#define MMHUB_BASE__INST5_SEG0 0 500#define MMHUB_BASE__INST5_SEG1 0 501#define MMHUB_BASE__INST5_SEG2 0 502#define MMHUB_BASE__INST5_SEG3 0 503#define MMHUB_BASE__INST5_SEG4 0 504#define MMHUB_BASE__INST5_SEG5 0 505 506#define MP0_BASE__INST0_SEG0 0x00016000 507#define MP0_BASE__INST0_SEG1 0 508#define MP0_BASE__INST0_SEG2 0 509#define MP0_BASE__INST0_SEG3 0 510#define MP0_BASE__INST0_SEG4 0 511#define MP0_BASE__INST0_SEG5 0 512 513#define MP0_BASE__INST1_SEG0 0 514#define MP0_BASE__INST1_SEG1 0 515#define MP0_BASE__INST1_SEG2 0 516#define MP0_BASE__INST1_SEG3 0 517#define MP0_BASE__INST1_SEG4 0 518#define MP0_BASE__INST1_SEG5 0 519 520#define MP0_BASE__INST2_SEG0 0 521#define MP0_BASE__INST2_SEG1 0 522#define MP0_BASE__INST2_SEG2 0 523#define MP0_BASE__INST2_SEG3 0 524#define MP0_BASE__INST2_SEG4 0 525#define MP0_BASE__INST2_SEG5 0 526 527#define MP0_BASE__INST3_SEG0 0 528#define MP0_BASE__INST3_SEG1 0 529#define MP0_BASE__INST3_SEG2 0 530#define MP0_BASE__INST3_SEG3 0 531#define MP0_BASE__INST3_SEG4 0 532#define MP0_BASE__INST3_SEG5 0 533 534#define MP0_BASE__INST4_SEG0 0 535#define MP0_BASE__INST4_SEG1 0 536#define MP0_BASE__INST4_SEG2 0 537#define MP0_BASE__INST4_SEG3 0 538#define MP0_BASE__INST4_SEG4 0 539#define MP0_BASE__INST4_SEG5 0 540 541#define MP0_BASE__INST5_SEG0 0 542#define MP0_BASE__INST5_SEG1 0 543#define MP0_BASE__INST5_SEG2 0 544#define MP0_BASE__INST5_SEG3 0 545#define MP0_BASE__INST5_SEG4 0 546#define MP0_BASE__INST5_SEG5 0 547 548#define MP1_BASE__INST0_SEG0 0x00016000 549#define MP1_BASE__INST0_SEG1 0 550#define MP1_BASE__INST0_SEG2 0 551#define MP1_BASE__INST0_SEG3 0 552#define MP1_BASE__INST0_SEG4 0 553#define MP1_BASE__INST0_SEG5 0 554 555#define MP1_BASE__INST1_SEG0 0 556#define MP1_BASE__INST1_SEG1 0 557#define MP1_BASE__INST1_SEG2 0 558#define MP1_BASE__INST1_SEG3 0 559#define MP1_BASE__INST1_SEG4 0 560#define MP1_BASE__INST1_SEG5 0 561 562#define MP1_BASE__INST2_SEG0 0 563#define MP1_BASE__INST2_SEG1 0 564#define MP1_BASE__INST2_SEG2 0 565#define MP1_BASE__INST2_SEG3 0 566#define MP1_BASE__INST2_SEG4 0 567#define MP1_BASE__INST2_SEG5 0 568 569#define MP1_BASE__INST3_SEG0 0 570#define MP1_BASE__INST3_SEG1 0 571#define MP1_BASE__INST3_SEG2 0 572#define MP1_BASE__INST3_SEG3 0 573#define MP1_BASE__INST3_SEG4 0 574#define MP1_BASE__INST3_SEG5 0 575 576#define MP1_BASE__INST4_SEG0 0 577#define MP1_BASE__INST4_SEG1 0 578#define MP1_BASE__INST4_SEG2 0 579#define MP1_BASE__INST4_SEG3 0 580#define MP1_BASE__INST4_SEG4 0 581#define MP1_BASE__INST4_SEG5 0 582 583#define MP1_BASE__INST5_SEG0 0 584#define MP1_BASE__INST5_SEG1 0 585#define MP1_BASE__INST5_SEG2 0 586#define MP1_BASE__INST5_SEG3 0 587#define MP1_BASE__INST5_SEG4 0 588#define MP1_BASE__INST5_SEG5 0 589 590#define NBIO_BASE__INST0_SEG0 0x00000000 591#define NBIO_BASE__INST0_SEG1 0x00000014 592#define NBIO_BASE__INST0_SEG2 0x00000D20 593#define NBIO_BASE__INST0_SEG3 0x00010400 594#define NBIO_BASE__INST0_SEG4 0 595#define NBIO_BASE__INST0_SEG5 0 596 597#define NBIO_BASE__INST1_SEG0 0 598#define NBIO_BASE__INST1_SEG1 0 599#define NBIO_BASE__INST1_SEG2 0 600#define NBIO_BASE__INST1_SEG3 0 601#define NBIO_BASE__INST1_SEG4 0 602#define NBIO_BASE__INST1_SEG5 0 603 604#define NBIO_BASE__INST2_SEG0 0 605#define NBIO_BASE__INST2_SEG1 0 606#define NBIO_BASE__INST2_SEG2 0 607#define NBIO_BASE__INST2_SEG3 0 608#define NBIO_BASE__INST2_SEG4 0 609#define NBIO_BASE__INST2_SEG5 0 610 611#define NBIO_BASE__INST3_SEG0 0 612#define NBIO_BASE__INST3_SEG1 0 613#define NBIO_BASE__INST3_SEG2 0 614#define NBIO_BASE__INST3_SEG3 0 615#define NBIO_BASE__INST3_SEG4 0 616#define NBIO_BASE__INST3_SEG5 0 617 618#define NBIO_BASE__INST4_SEG0 0 619#define NBIO_BASE__INST4_SEG1 0 620#define NBIO_BASE__INST4_SEG2 0 621#define NBIO_BASE__INST4_SEG3 0 622#define NBIO_BASE__INST4_SEG4 0 623#define NBIO_BASE__INST4_SEG5 0 624 625#define NBIO_BASE__INST5_SEG0 0 626#define NBIO_BASE__INST5_SEG1 0 627#define NBIO_BASE__INST5_SEG2 0 628#define NBIO_BASE__INST5_SEG3 0 629#define NBIO_BASE__INST5_SEG4 0 630#define NBIO_BASE__INST5_SEG5 0 631 632#define OSSSYS_BASE__INST0_SEG0 0x000010A0 633#define OSSSYS_BASE__INST0_SEG1 0 634#define OSSSYS_BASE__INST0_SEG2 0 635#define OSSSYS_BASE__INST0_SEG3 0 636#define OSSSYS_BASE__INST0_SEG4 0 637#define OSSSYS_BASE__INST0_SEG5 0 638 639#define OSSSYS_BASE__INST1_SEG0 0 640#define OSSSYS_BASE__INST1_SEG1 0 641#define OSSSYS_BASE__INST1_SEG2 0 642#define OSSSYS_BASE__INST1_SEG3 0 643#define OSSSYS_BASE__INST1_SEG4 0 644#define OSSSYS_BASE__INST1_SEG5 0 645 646#define OSSSYS_BASE__INST2_SEG0 0 647#define OSSSYS_BASE__INST2_SEG1 0 648#define OSSSYS_BASE__INST2_SEG2 0 649#define OSSSYS_BASE__INST2_SEG3 0 650#define OSSSYS_BASE__INST2_SEG4 0 651#define OSSSYS_BASE__INST2_SEG5 0 652 653#define OSSSYS_BASE__INST3_SEG0 0 654#define OSSSYS_BASE__INST3_SEG1 0 655#define OSSSYS_BASE__INST3_SEG2 0 656#define OSSSYS_BASE__INST3_SEG3 0 657#define OSSSYS_BASE__INST3_SEG4 0 658#define OSSSYS_BASE__INST3_SEG5 0 659 660#define OSSSYS_BASE__INST4_SEG0 0 661#define OSSSYS_BASE__INST4_SEG1 0 662#define OSSSYS_BASE__INST4_SEG2 0 663#define OSSSYS_BASE__INST4_SEG3 0 664#define OSSSYS_BASE__INST4_SEG4 0 665#define OSSSYS_BASE__INST4_SEG5 0 666 667#define OSSSYS_BASE__INST5_SEG0 0 668#define OSSSYS_BASE__INST5_SEG1 0 669#define OSSSYS_BASE__INST5_SEG2 0 670#define OSSSYS_BASE__INST5_SEG3 0 671#define OSSSYS_BASE__INST5_SEG4 0 672#define OSSSYS_BASE__INST5_SEG5 0 673 674#define SDMA0_BASE__INST0_SEG0 0x00001260 675#define SDMA0_BASE__INST0_SEG1 0 676#define SDMA0_BASE__INST0_SEG2 0 677#define SDMA0_BASE__INST0_SEG3 0 678#define SDMA0_BASE__INST0_SEG4 0 679#define SDMA0_BASE__INST0_SEG5 0 680 681#define SDMA0_BASE__INST1_SEG0 0 682#define SDMA0_BASE__INST1_SEG1 0 683#define SDMA0_BASE__INST1_SEG2 0 684#define SDMA0_BASE__INST1_SEG3 0 685#define SDMA0_BASE__INST1_SEG4 0 686#define SDMA0_BASE__INST1_SEG5 0 687 688#define SDMA0_BASE__INST2_SEG0 0 689#define SDMA0_BASE__INST2_SEG1 0 690#define SDMA0_BASE__INST2_SEG2 0 691#define SDMA0_BASE__INST2_SEG3 0 692#define SDMA0_BASE__INST2_SEG4 0 693#define SDMA0_BASE__INST2_SEG5 0 694 695#define SDMA0_BASE__INST3_SEG0 0 696#define SDMA0_BASE__INST3_SEG1 0 697#define SDMA0_BASE__INST3_SEG2 0 698#define SDMA0_BASE__INST3_SEG3 0 699#define SDMA0_BASE__INST3_SEG4 0 700#define SDMA0_BASE__INST3_SEG5 0 701 702#define SDMA0_BASE__INST4_SEG0 0 703#define SDMA0_BASE__INST4_SEG1 0 704#define SDMA0_BASE__INST4_SEG2 0 705#define SDMA0_BASE__INST4_SEG3 0 706#define SDMA0_BASE__INST4_SEG4 0 707#define SDMA0_BASE__INST4_SEG5 0 708 709#define SDMA0_BASE__INST5_SEG0 0 710#define SDMA0_BASE__INST5_SEG1 0 711#define SDMA0_BASE__INST5_SEG2 0 712#define SDMA0_BASE__INST5_SEG3 0 713#define SDMA0_BASE__INST5_SEG4 0 714#define SDMA0_BASE__INST5_SEG5 0 715 716#define SDMA1_BASE__INST0_SEG0 0x00001860 717#define SDMA1_BASE__INST0_SEG1 0 718#define SDMA1_BASE__INST0_SEG2 0 719#define SDMA1_BASE__INST0_SEG3 0 720#define SDMA1_BASE__INST0_SEG4 0 721#define SDMA1_BASE__INST0_SEG5 0 722 723#define SDMA1_BASE__INST1_SEG0 0 724#define SDMA1_BASE__INST1_SEG1 0 725#define SDMA1_BASE__INST1_SEG2 0 726#define SDMA1_BASE__INST1_SEG3 0 727#define SDMA1_BASE__INST1_SEG4 0 728#define SDMA1_BASE__INST1_SEG5 0 729 730#define SDMA1_BASE__INST2_SEG0 0 731#define SDMA1_BASE__INST2_SEG1 0 732#define SDMA1_BASE__INST2_SEG2 0 733#define SDMA1_BASE__INST2_SEG3 0 734#define SDMA1_BASE__INST2_SEG4 0 735#define SDMA1_BASE__INST2_SEG5 0 736 737#define SDMA1_BASE__INST3_SEG0 0 738#define SDMA1_BASE__INST3_SEG1 0 739#define SDMA1_BASE__INST3_SEG2 0 740#define SDMA1_BASE__INST3_SEG3 0 741#define SDMA1_BASE__INST3_SEG4 0 742#define SDMA1_BASE__INST3_SEG5 0 743 744#define SDMA1_BASE__INST4_SEG0 0 745#define SDMA1_BASE__INST4_SEG1 0 746#define SDMA1_BASE__INST4_SEG2 0 747#define SDMA1_BASE__INST4_SEG3 0 748#define SDMA1_BASE__INST4_SEG4 0 749#define SDMA1_BASE__INST4_SEG5 0 750 751#define SDMA1_BASE__INST5_SEG0 0 752#define SDMA1_BASE__INST5_SEG1 0 753#define SDMA1_BASE__INST5_SEG2 0 754#define SDMA1_BASE__INST5_SEG3 0 755#define SDMA1_BASE__INST5_SEG4 0 756#define SDMA1_BASE__INST5_SEG5 0 757 758#define SMUIO_BASE__INST0_SEG0 0x00016800 759#define SMUIO_BASE__INST0_SEG1 0x00016A00 760#define SMUIO_BASE__INST0_SEG2 0 761#define SMUIO_BASE__INST0_SEG3 0 762#define SMUIO_BASE__INST0_SEG4 0 763#define SMUIO_BASE__INST0_SEG5 0 764 765#define SMUIO_BASE__INST1_SEG0 0 766#define SMUIO_BASE__INST1_SEG1 0 767#define SMUIO_BASE__INST1_SEG2 0 768#define SMUIO_BASE__INST1_SEG3 0 769#define SMUIO_BASE__INST1_SEG4 0 770#define SMUIO_BASE__INST1_SEG5 0 771 772#define SMUIO_BASE__INST2_SEG0 0 773#define SMUIO_BASE__INST2_SEG1 0 774#define SMUIO_BASE__INST2_SEG2 0 775#define SMUIO_BASE__INST2_SEG3 0 776#define SMUIO_BASE__INST2_SEG4 0 777#define SMUIO_BASE__INST2_SEG5 0 778 779#define SMUIO_BASE__INST3_SEG0 0 780#define SMUIO_BASE__INST3_SEG1 0 781#define SMUIO_BASE__INST3_SEG2 0 782#define SMUIO_BASE__INST3_SEG3 0 783#define SMUIO_BASE__INST3_SEG4 0 784#define SMUIO_BASE__INST3_SEG5 0 785 786#define SMUIO_BASE__INST4_SEG0 0 787#define SMUIO_BASE__INST4_SEG1 0 788#define SMUIO_BASE__INST4_SEG2 0 789#define SMUIO_BASE__INST4_SEG3 0 790#define SMUIO_BASE__INST4_SEG4 0 791#define SMUIO_BASE__INST4_SEG5 0 792 793#define SMUIO_BASE__INST5_SEG0 0 794#define SMUIO_BASE__INST5_SEG1 0 795#define SMUIO_BASE__INST5_SEG2 0 796#define SMUIO_BASE__INST5_SEG3 0 797#define SMUIO_BASE__INST5_SEG4 0 798#define SMUIO_BASE__INST5_SEG5 0 799 800#define THM_BASE__INST0_SEG0 0x00016600 801#define THM_BASE__INST0_SEG1 0 802#define THM_BASE__INST0_SEG2 0 803#define THM_BASE__INST0_SEG3 0 804#define THM_BASE__INST0_SEG4 0 805#define THM_BASE__INST0_SEG5 0 806 807#define THM_BASE__INST1_SEG0 0 808#define THM_BASE__INST1_SEG1 0 809#define THM_BASE__INST1_SEG2 0 810#define THM_BASE__INST1_SEG3 0 811#define THM_BASE__INST1_SEG4 0 812#define THM_BASE__INST1_SEG5 0 813 814#define THM_BASE__INST2_SEG0 0 815#define THM_BASE__INST2_SEG1 0 816#define THM_BASE__INST2_SEG2 0 817#define THM_BASE__INST2_SEG3 0 818#define THM_BASE__INST2_SEG4 0 819#define THM_BASE__INST2_SEG5 0 820 821#define THM_BASE__INST3_SEG0 0 822#define THM_BASE__INST3_SEG1 0 823#define THM_BASE__INST3_SEG2 0 824#define THM_BASE__INST3_SEG3 0 825#define THM_BASE__INST3_SEG4 0 826#define THM_BASE__INST3_SEG5 0 827 828#define THM_BASE__INST4_SEG0 0 829#define THM_BASE__INST4_SEG1 0 830#define THM_BASE__INST4_SEG2 0 831#define THM_BASE__INST4_SEG3 0 832#define THM_BASE__INST4_SEG4 0 833#define THM_BASE__INST4_SEG5 0 834 835#define THM_BASE__INST5_SEG0 0 836#define THM_BASE__INST5_SEG1 0 837#define THM_BASE__INST5_SEG2 0 838#define THM_BASE__INST5_SEG3 0 839#define THM_BASE__INST5_SEG4 0 840#define THM_BASE__INST5_SEG5 0 841 842#define UMC_BASE__INST0_SEG0 0x00014000 843#define UMC_BASE__INST0_SEG1 0 844#define UMC_BASE__INST0_SEG2 0 845#define UMC_BASE__INST0_SEG3 0 846#define UMC_BASE__INST0_SEG4 0 847#define UMC_BASE__INST0_SEG5 0 848 849#define UMC_BASE__INST1_SEG0 0 850#define UMC_BASE__INST1_SEG1 0 851#define UMC_BASE__INST1_SEG2 0 852#define UMC_BASE__INST1_SEG3 0 853#define UMC_BASE__INST1_SEG4 0 854#define UMC_BASE__INST1_SEG5 0 855 856#define UMC_BASE__INST2_SEG0 0 857#define UMC_BASE__INST2_SEG1 0 858#define UMC_BASE__INST2_SEG2 0 859#define UMC_BASE__INST2_SEG3 0 860#define UMC_BASE__INST2_SEG4 0 861#define UMC_BASE__INST2_SEG5 0 862 863#define UMC_BASE__INST3_SEG0 0 864#define UMC_BASE__INST3_SEG1 0 865#define UMC_BASE__INST3_SEG2 0 866#define UMC_BASE__INST3_SEG3 0 867#define UMC_BASE__INST3_SEG4 0 868#define UMC_BASE__INST3_SEG5 0 869 870#define UMC_BASE__INST4_SEG0 0 871#define UMC_BASE__INST4_SEG1 0 872#define UMC_BASE__INST4_SEG2 0 873#define UMC_BASE__INST4_SEG3 0 874#define UMC_BASE__INST4_SEG4 0 875#define UMC_BASE__INST4_SEG5 0 876 877#define UMC_BASE__INST5_SEG0 0 878#define UMC_BASE__INST5_SEG1 0 879#define UMC_BASE__INST5_SEG2 0 880#define UMC_BASE__INST5_SEG3 0 881#define UMC_BASE__INST5_SEG4 0 882#define UMC_BASE__INST5_SEG5 0 883 884#define UVD_BASE__INST0_SEG0 0x00007800 885#define UVD_BASE__INST0_SEG1 0x00007E00 886#define UVD_BASE__INST0_SEG2 0 887#define UVD_BASE__INST0_SEG3 0 888#define UVD_BASE__INST0_SEG4 0 889#define UVD_BASE__INST0_SEG5 0 890 891#define UVD_BASE__INST1_SEG0 0 892#define UVD_BASE__INST1_SEG1 0x00009000 893#define UVD_BASE__INST1_SEG2 0 894#define UVD_BASE__INST1_SEG3 0 895#define UVD_BASE__INST1_SEG4 0 896#define UVD_BASE__INST1_SEG5 0 897 898#define UVD_BASE__INST2_SEG0 0 899#define UVD_BASE__INST2_SEG1 0 900#define UVD_BASE__INST2_SEG2 0 901#define UVD_BASE__INST2_SEG3 0 902#define UVD_BASE__INST2_SEG4 0 903#define UVD_BASE__INST2_SEG5 0 904 905#define UVD_BASE__INST3_SEG0 0 906#define UVD_BASE__INST3_SEG1 0 907#define UVD_BASE__INST3_SEG2 0 908#define UVD_BASE__INST3_SEG3 0 909#define UVD_BASE__INST3_SEG4 0 910#define UVD_BASE__INST3_SEG5 0 911 912#define UVD_BASE__INST4_SEG0 0 913#define UVD_BASE__INST4_SEG1 0 914#define UVD_BASE__INST4_SEG2 0 915#define UVD_BASE__INST4_SEG3 0 916#define UVD_BASE__INST4_SEG4 0 917#define UVD_BASE__INST4_SEG5 0 918 919#define UVD_BASE__INST5_SEG0 0 920#define UVD_BASE__INST5_SEG1 0 921#define UVD_BASE__INST5_SEG2 0 922#define UVD_BASE__INST5_SEG3 0 923#define UVD_BASE__INST5_SEG4 0 924#define UVD_BASE__INST5_SEG5 0 925 926#define VCE_BASE__INST0_SEG0 0x00008800 927#define VCE_BASE__INST0_SEG1 0 928#define VCE_BASE__INST0_SEG2 0 929#define VCE_BASE__INST0_SEG3 0 930#define VCE_BASE__INST0_SEG4 0 931#define VCE_BASE__INST0_SEG5 0 932 933#define VCE_BASE__INST1_SEG0 0 934#define VCE_BASE__INST1_SEG1 0 935#define VCE_BASE__INST1_SEG2 0 936#define VCE_BASE__INST1_SEG3 0 937#define VCE_BASE__INST1_SEG4 0 938#define VCE_BASE__INST1_SEG5 0 939 940#define VCE_BASE__INST2_SEG0 0 941#define VCE_BASE__INST2_SEG1 0 942#define VCE_BASE__INST2_SEG2 0 943#define VCE_BASE__INST2_SEG3 0 944#define VCE_BASE__INST2_SEG4 0 945#define VCE_BASE__INST2_SEG5 0 946 947#define VCE_BASE__INST3_SEG0 0 948#define VCE_BASE__INST3_SEG1 0 949#define VCE_BASE__INST3_SEG2 0 950#define VCE_BASE__INST3_SEG3 0 951#define VCE_BASE__INST3_SEG4 0 952#define VCE_BASE__INST3_SEG5 0 953 954#define VCE_BASE__INST4_SEG0 0 955#define VCE_BASE__INST4_SEG1 0 956#define VCE_BASE__INST4_SEG2 0 957#define VCE_BASE__INST4_SEG3 0 958#define VCE_BASE__INST4_SEG4 0 959#define VCE_BASE__INST4_SEG5 0 960 961#define VCE_BASE__INST5_SEG0 0 962#define VCE_BASE__INST5_SEG1 0 963#define VCE_BASE__INST5_SEG2 0 964#define VCE_BASE__INST5_SEG3 0 965#define VCE_BASE__INST5_SEG4 0 966#define VCE_BASE__INST5_SEG5 0 967 968#define XDMA_BASE__INST0_SEG0 0x00003400 969#define XDMA_BASE__INST0_SEG1 0 970#define XDMA_BASE__INST0_SEG2 0 971#define XDMA_BASE__INST0_SEG3 0 972#define XDMA_BASE__INST0_SEG4 0 973#define XDMA_BASE__INST0_SEG5 0 974 975#define XDMA_BASE__INST1_SEG0 0 976#define XDMA_BASE__INST1_SEG1 0 977#define XDMA_BASE__INST1_SEG2 0 978#define XDMA_BASE__INST1_SEG3 0 979#define XDMA_BASE__INST1_SEG4 0 980#define XDMA_BASE__INST1_SEG5 0 981 982#define XDMA_BASE__INST2_SEG0 0 983#define XDMA_BASE__INST2_SEG1 0 984#define XDMA_BASE__INST2_SEG2 0 985#define XDMA_BASE__INST2_SEG3 0 986#define XDMA_BASE__INST2_SEG4 0 987#define XDMA_BASE__INST2_SEG5 0 988 989#define XDMA_BASE__INST3_SEG0 0 990#define XDMA_BASE__INST3_SEG1 0 991#define XDMA_BASE__INST3_SEG2 0 992#define XDMA_BASE__INST3_SEG3 0 993#define XDMA_BASE__INST3_SEG4 0 994#define XDMA_BASE__INST3_SEG5 0 995 996#define XDMA_BASE__INST4_SEG0 0 997#define XDMA_BASE__INST4_SEG1 0 998#define XDMA_BASE__INST4_SEG2 0 999#define XDMA_BASE__INST4_SEG3 0 1000#define XDMA_BASE__INST4_SEG4 0 1001#define XDMA_BASE__INST4_SEG5 0 1002 1003#define XDMA_BASE__INST5_SEG0 0 1004#define XDMA_BASE__INST5_SEG1 0 1005#define XDMA_BASE__INST5_SEG2 0 1006#define XDMA_BASE__INST5_SEG3 0 1007#define XDMA_BASE__INST5_SEG4 0 1008#define XDMA_BASE__INST5_SEG5 0 1009 1010#define RSMU_BASE__INST0_SEG0 0x00012000 1011#define RSMU_BASE__INST0_SEG1 0 1012#define RSMU_BASE__INST0_SEG2 0 1013#define RSMU_BASE__INST0_SEG3 0 1014#define RSMU_BASE__INST0_SEG4 0 1015#define RSMU_BASE__INST0_SEG5 0 1016 1017#define RSMU_BASE__INST1_SEG0 0 1018#define RSMU_BASE__INST1_SEG1 0 1019#define RSMU_BASE__INST1_SEG2 0 1020#define RSMU_BASE__INST1_SEG3 0 1021#define RSMU_BASE__INST1_SEG4 0 1022#define RSMU_BASE__INST1_SEG5 0 1023 1024#define RSMU_BASE__INST2_SEG0 0 1025#define RSMU_BASE__INST2_SEG1 0 1026#define RSMU_BASE__INST2_SEG2 0 1027#define RSMU_BASE__INST2_SEG3 0 1028#define RSMU_BASE__INST2_SEG4 0 1029#define RSMU_BASE__INST2_SEG5 0 1030 1031#define RSMU_BASE__INST3_SEG0 0 1032#define RSMU_BASE__INST3_SEG1 0 1033#define RSMU_BASE__INST3_SEG2 0 1034#define RSMU_BASE__INST3_SEG3 0 1035#define RSMU_BASE__INST3_SEG4 0 1036#define RSMU_BASE__INST3_SEG5 0 1037 1038#define RSMU_BASE__INST4_SEG0 0 1039#define RSMU_BASE__INST4_SEG1 0 1040#define RSMU_BASE__INST4_SEG2 0 1041#define RSMU_BASE__INST4_SEG3 0 1042#define RSMU_BASE__INST4_SEG4 0 1043#define RSMU_BASE__INST4_SEG5 0 1044 1045#define RSMU_BASE__INST5_SEG0 0 1046#define RSMU_BASE__INST5_SEG1 0 1047#define RSMU_BASE__INST5_SEG2 0 1048#define RSMU_BASE__INST5_SEG3 0 1049#define RSMU_BASE__INST5_SEG4 0 1050#define RSMU_BASE__INST5_SEG5 0 1051 1052#endif 1053 1054