Searched refs:MOI (Results 1 - 10 of 10) sorted by relevance
/openbsd-current/gnu/llvm/llvm/lib/CodeGen/ |
H A D | StackMaps.cpp | 205 StackMaps::parseOperand(MachineInstr::const_mop_iterator MOI, argument 209 if (MOI->isImm()) { 210 switch (MOI->getImm()) { 219 Register Reg = (++MOI)->getReg(); 220 int64_t Imm = (++MOI)->getImm(); 226 int64_t Size = (++MOI)->getImm(); 228 Register Reg = (++MOI)->getReg(); 229 int64_t Imm = (++MOI)->getImm(); 235 ++MOI; 236 assert(MOI 405 parseStatepointOpers(const MachineInstr &MI, MachineInstr::const_mop_iterator MOI, MachineInstr::const_mop_iterator MOE, LocationVec &Locations, LiveOutVec &LiveOuts) argument 556 auto MOI = std::next(MI.operands_begin(), opers.getStackMapStartIdx()); local [all...] |
H A D | LiveInterval.cpp | 890 for (ConstMIBundleOperands MOI(*MI); MOI.isValid(); ++MOI) { 891 if (!MOI->isReg() || !MOI->isDef()) 893 if (MOI->getReg() != Reg) 895 LaneBitmask OrigMask = TRI.getSubRegIndexLaneMask(MOI->getSubReg());
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H A D | MachineVerifier.cpp | 3015 for (ConstMIBundleOperands MOI(*MI); MOI.isValid(); ++MOI) { 3016 if (!MOI->isReg() || !MOI->isDef()) 3019 if (MOI->getReg() != Reg) 3022 if (!MOI->getReg().isPhysical() || !TRI->hasRegUnit(MOI->getReg(), Reg)) 3026 (TRI->getSubRegIndexLaneMask(MOI->getSubReg()) & LaneMask).none()) 3029 if (MOI [all...] |
H A D | MachineTraceMetrics.cpp | 898 for (MachineInstr::const_mop_iterator MOI = MI.operands_begin(), 900 MOI != MOE; ++MOI) { 901 const MachineOperand &MO = *MOI; 908 ReadOps.push_back(MI.getOperandNo(MOI)); 922 DepHeight += SchedModel.computeOperandLatency(&MI, MI.getOperandNo(MOI),
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H A D | MachinePipeliner.cpp | 868 for (MachineInstr::mop_iterator MOI = MI->operands_begin(), 870 MOI != MOE; ++MOI) { 871 if (!MOI->isReg()) 873 Register Reg = MOI->getReg(); 874 if (MOI->isDef()) { 896 } else if (MOI->isUse()) { 906 ST.adjustSchedDependency(SU, 0, &I, MI->getOperandNo(MOI), Dep);
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/openbsd-current/gnu/llvm/llvm/lib/Target/AMDGPU/ |
H A D | SIMemoryLegalizer.cpp | 584 bool expandLoad(const SIMemOpInfo &MOI, 588 bool expandStore(const SIMemOpInfo &MOI, 592 bool expandAtomicFence(const SIMemOpInfo &MOI, 596 bool expandAtomicCmpxchgOrRmw(const SIMemOpInfo &MOI, 2126 bool SIMemoryLegalizer::expandLoad(const SIMemOpInfo &MOI, argument 2132 if (MOI.isAtomic()) { 2133 if (MOI.getOrdering() == AtomicOrdering::Monotonic || 2134 MOI.getOrdering() == AtomicOrdering::Acquire || 2135 MOI.getOrdering() == AtomicOrdering::SequentiallyConsistent) { 2136 Changed |= CC->enableLoadCacheBypass(MI, MOI 2171 expandStore(const SIMemOpInfo &MOI, MachineBasicBlock::iterator &MI) argument 2204 expandAtomicFence(const SIMemOpInfo &MOI, MachineBasicBlock::iterator &MI) argument 2246 expandAtomicCmpxchgOrRmw(const SIMemOpInfo &MOI, MachineBasicBlock::iterator &MI) argument [all...] |
H A D | R600EmitClauseMarkers.cpp | 186 MOI = Def->operands_begin(), 187 MOE = Def->operands_end(); MOI != MOE; ++MOI) { 188 if (!MOI->isReg() || !MOI->isDef() || 189 TRI.isPhysRegLiveAcrossClauses(MOI->getReg())) 213 if (UseI->readsRegister(MOI->getReg(), &TRI)) 217 if (UseI != Def && UseI->killsRegister(MOI->getReg(), &TRI))
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/openbsd-current/gnu/llvm/llvm/lib/Target/AVR/MCTargetDesc/ |
H A D | AVRInstPrinter.cpp | 103 const MCOperandInfo &MOI = this->MII.get(MI->getOpcode()).operands()[OpNo]; local 104 if (MOI.RegClass == AVR::ZREGRegClassID) { 124 bool isPtrReg = (MOI.RegClass == AVR::PTRREGSRegClassID) || 125 (MOI.RegClass == AVR::PTRDISPREGSRegClassID) || 126 (MOI.RegClass == AVR::ZREGRegClassID);
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/openbsd-current/gnu/llvm/llvm/include/llvm/CodeGen/ |
H A D | StackMaps.h | 370 parseOperand(MachineInstr::const_mop_iterator MOI, 377 MachineInstr::const_mop_iterator MOI, 398 MachineInstr::const_mop_iterator MOI,
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/openbsd-current/gnu/llvm/llvm/lib/Target/Hexagon/ |
H A D | HexagonEarlyIfConv.cpp | 724 MachineInstr::mop_iterator MOI = MI->operands_begin(); local 726 MIB.add(*MOI); 727 ++MOI; 730 for (const MachineOperand &MO : make_range(MOI, MI->operands_end()))
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