Searched refs:MISC_CLK_CTRL__ZCLK_SEL_MASK (Results 1 - 11 of 11) sorted by relevance
| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
| H A D | amdgpu_ci_baco.c | 121 { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__ZCLK_SEL_MASK, MISC_CLK_CTRL__ZCLK_SEL__SHIFT, 0, 0x2 },
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| H A D | amdgpu_fiji_baco.c | 104 { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__ZCLK_SEL_MASK, MISC_CLK_CTRL__ZCLK_SEL__SHIFT, 0, 0x1 },
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| H A D | amdgpu_polaris_baco.c | 107 { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__ZCLK_SEL_MASK, MISC_CLK_CTRL__ZCLK_SEL__SHIFT, 0, 0x1 },
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| H A D | amdgpu_tonga_baco.c | 112 { CMD_READMODIFYWRITE, mmGCK_SMC_IND_DATA, MISC_CLK_CTRL__ZCLK_SEL_MASK, MISC_CLK_CTRL__ZCLK_SEL__SHIFT, 0, 0x1 },
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | amdgpu_cik.c | 1764 MISC_CLK_CTRL__ZCLK_SEL_MASK);
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/smu/ |
| H A D | smu_7_0_0_sh_mask.h | 273 #define MISC_CLK_CTRL__ZCLK_SEL_MASK 0xff00 macro
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| H A D | smu_7_1_1_sh_mask.h | 271 #define MISC_CLK_CTRL__ZCLK_SEL_MASK 0xff00 macro
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| H A D | smu_7_1_3_sh_mask.h | 299 #define MISC_CLK_CTRL__ZCLK_SEL_MASK 0xff00 macro
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| H A D | smu_7_1_2_sh_mask.h | 271 #define MISC_CLK_CTRL__ZCLK_SEL_MASK 0xff00 macro
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| H A D | smu_7_1_0_sh_mask.h | 269 #define MISC_CLK_CTRL__ZCLK_SEL_MASK 0xff00 macro
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| H A D | smu_7_0_1_sh_mask.h | 271 #define MISC_CLK_CTRL__ZCLK_SEL_MASK 0xff00 macro
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