Searched refs:LEVEL0_MPLL_POST_DIV_MASK (Results 1 - 2 of 2) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/radeon/
H A Drv6xxd.h82 # define LEVEL0_MPLL_POST_DIV_MASK (0xff << 0) macro
H A Dradeon_rv6xx_dpm.c388 LEVEL0_MPLL_POST_DIV(divider), ~LEVEL0_MPLL_POST_DIV_MASK);

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