Searched refs:GCSC_DIVIL_MSR_BASE (Results 1 - 1 of 1) sorted by relevance

/netbsd-current/sys/arch/evbmips/loongson/dev/
H A Dglxreg.h31 #define GCSC_DIVIL_MSR_BASE 0x51400000 macro
182 #define GCSC_DIVIL_GLD_MSR_CAP (GCSC_DIVIL_MSR_BASE + 0x00)
183 #define GCSC_DIVIL_GLD_MSR_CONFIG (GCSC_DIVIL_MSR_BASE + 0x01)
184 #define GCSC_DIVIL_GLD_MSR_SMI (GCSC_DIVIL_MSR_BASE + 0x02)
185 #define GCSC_DIVIL_GLD_MSR_ERROR (GCSC_DIVIL_MSR_BASE + 0x03)
186 #define GCSC_DIVIL_GLD_MSR_PM (GCSC_DIVIL_MSR_BASE + 0x04)
187 #define GCSC_DIVIL_GLD_MSR_DIAG (GCSC_DIVIL_MSR_BASE + 0x05)
189 #define GCSC_DIVIL_LBAR_IRQ (GCSC_DIVIL_MSR_BASE + 0x08)
190 #define GCSC_DIVIL_LBAR_KEL (GCSC_DIVIL_MSR_BASE + 0x09)
191 #define GCSC_DIVIL_LBAR_SMB (GCSC_DIVIL_MSR_BASE
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