1/* $OpenBSD: glxreg.h,v 1.1 2010/10/14 21:23:05 pirofti Exp $ */ 2 3/* 4 * Copyright (c) 2009 Miodrag Vallat. 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19/* 20 * AMD 5536 Geode companion chip MSR registers 21 */ 22 23/* 24 * Base addresses of the MSR groups. 25 */ 26 27#define GCSC_SB_MSR_BASE 0x51000000 28#define GCSC_GLIU_MSR_BASE 0x51010000 29#define GCSC_USB_MSR_BASE 0x51200000 30#define GCSC_IDE_MSR_BASE 0x51300000 31#define GCSC_DIVIL_MSR_BASE 0x51400000 32#define GCSC_ACC_MSR_BASE 0x51500000 33#define GCSC_GLCP_MSR_BASE 0x51700000 34 35/* 36 * GeodeLink Interface Unit (GLIU) 37 */ 38 39#define GCSC_GLIU_GLD_MSR_CAP (GCSC_GLIU_MSR_BASE + 0x00) 40#define GCSC_GLIU_GLD_MSR_CONFIG (GCSC_GLIU_MSR_BASE + 0x01) 41#define GCSC_GLIU_GLD_MSR_SMI (GCSC_GLIU_MSR_BASE + 0x02) 42#define GCSC_GLIU_GLD_MSR_ERROR (GCSC_GLIU_MSR_BASE + 0x03) 43#define GCSC_GLIU_GLD_MSR_PM (GCSC_GLIU_MSR_BASE + 0x04) 44#define GCSC_GLIU_GLD_MSR_DIAG (GCSC_GLIU_MSR_BASE + 0x05) 45 46#define GCSC_GLIU_P2D_BM0 (GCSC_GLIU_MSR_BASE + 0x20) 47#define GCSC_GLIU_P2D_BM1 (GCSC_GLIU_MSR_BASE + 0x21) 48#define GCSC_GLIU_P2D_BM2 (GCSC_GLIU_MSR_BASE + 0x22) 49#define GCSC_GLIU_P2D_BMK0 (GCSC_GLIU_MSR_BASE + 0x23) 50#define GCSC_GLIU_P2D_BMK1 (GCSC_GLIU_MSR_BASE + 0x24) 51#define GCSC_GLIU_P2D_BM3 (GCSC_GLIU_MSR_BASE + 0x25) 52#define GCSC_GLIU_P2D_BM4 (GCSC_GLIU_MSR_BASE + 0x26) 53 54#define GCSC_GLIU_COH (GCSC_GLIU_MSR_BASE + 0x80) 55#define GCSC_GLIU_PAE (GCSC_GLIU_MSR_BASE + 0x81) 56#define GCSC_GLIU_ARB (GCSC_GLIU_MSR_BASE + 0x82) 57#define GCSC_GLIU_ASMI (GCSC_GLIU_MSR_BASE + 0x83) 58#define GCSC_GLIU_AERR (GCSC_GLIU_MSR_BASE + 0x84) 59#define GCSC_GLIU_DEBUG (GCSC_GLIU_MSR_BASE + 0x85) 60#define GCSC_GLIU_PHY_CAP (GCSC_GLIU_MSR_BASE + 0x86) 61#define GCSC_GLIU_NOUT_RESP (GCSC_GLIU_MSR_BASE + 0x87) 62#define GCSC_GLIU_NOUT_WDATA (GCSC_GLIU_MSR_BASE + 0x88) 63#define GCSC_GLIU_WHOAMI (GCSC_GLIU_MSR_BASE + 0x8b) 64#define GCSC_GLIU_SLV_DIS (GCSC_GLIU_MSR_BASE + 0x8c) 65#define GCSC_GLIU_STATISTIC_CNT0 (GCSC_GLIU_MSR_BASE + 0xa0) 66#define GCSC_GLIU_STATISTIC_MASK0 (GCSC_GLIU_MSR_BASE + 0xa1) 67#define GCSC_GLIU_STATISTIC_ACTION0 (GCSC_GLIU_MSR_BASE + 0xa2) 68#define GCSC_GLIU_STATISTIC_CNT1 (GCSC_GLIU_MSR_BASE + 0xa4) 69#define GCSC_GLIU_STATISTIC_MASK1 (GCSC_GLIU_MSR_BASE + 0xa5) 70#define GCSC_GLIU_STATISTIC_ACTION1 (GCSC_GLIU_MSR_BASE + 0xa6) 71#define GCSC_GLIU_STATISTIC_CNT2 (GCSC_GLIU_MSR_BASE + 0xa8) 72#define GCSC_GLIU_STATISTIC_MASK2 (GCSC_GLIU_MSR_BASE + 0xa9) 73#define GCSC_GLIU_STATISTIC_ACTION2 (GCSC_GLIU_MSR_BASE + 0xaa) 74#define GCSC_GLIU_RQ_COMP_VAL (GCSC_GLIU_MSR_BASE + 0xc0) 75#define GCSC_GLIU_RQ_COMP_MASK (GCSC_GLIU_MSR_BASE + 0xc1) 76#define GCSC_GLIU_DA_COMP_VAL_LO (GCSC_GLIU_MSR_BASE + 0xd0) 77#define GCSC_GLIU_DA_COMP_VAL_HI (GCSC_GLIU_MSR_BASE + 0xd1) 78#define GCSC_GLIU_DA_COMP_MASK_LO (GCSC_GLIU_MSR_BASE + 0xd2) 79#define GCSC_GLIU_DA_COMP_MASK_HI (GCSC_GLIU_MSR_BASE + 0xd3) 80 81#define GCSC_GLIU_IOD_BM0 (GCSC_GLIU_MSR_BASE + 0xe0) 82#define GCSC_GLIU_IOD_BM1 (GCSC_GLIU_MSR_BASE + 0xe1) 83#define GCSC_GLIU_IOD_BM2 (GCSC_GLIU_MSR_BASE + 0xe2) 84#define GCSC_GLIU_IOD_BM3 (GCSC_GLIU_MSR_BASE + 0xe3) 85#define GCSC_GLIU_IOD_BM4 (GCSC_GLIU_MSR_BASE + 0xe4) 86#define GCSC_GLIU_IOD_BM5 (GCSC_GLIU_MSR_BASE + 0xe5) 87#define GCSC_GLIU_IOD_BM6 (GCSC_GLIU_MSR_BASE + 0xe6) 88#define GCSC_GLIU_IOD_BM7 (GCSC_GLIU_MSR_BASE + 0xe7) 89#define GCSC_GLIU_IOD_BM8 (GCSC_GLIU_MSR_BASE + 0xe8) 90#define GCSC_GLIU_IOD_BM9 (GCSC_GLIU_MSR_BASE + 0xe9) 91#define GCSC_GLIU_IOD_SC0 (GCSC_GLIU_MSR_BASE + 0xea) 92#define GCSC_GLIU_IOD_SC1 (GCSC_GLIU_MSR_BASE + 0xeb) 93#define GCSC_GLIU_IOD_SC2 (GCSC_GLIU_MSR_BASE + 0xec) 94#define GCSC_GLIU_IOD_SC3 (GCSC_GLIU_MSR_BASE + 0xed) 95#define GCSC_GLIU_IOD_SC4 (GCSC_GLIU_MSR_BASE + 0xee) 96#define GCSC_GLIU_IOD_SC5 (GCSC_GLIU_MSR_BASE + 0xef) 97#define GCSC_GLIU_IOD_SC6 (GCSC_GLIU_MSR_BASE + 0xf0) 98#define GCSC_GLIU_IOD_SC7 (GCSC_GLIU_MSR_BASE + 0xf1) 99 100/* 101 * GeodeLink PCI South Bridge (SB) 102 */ 103 104#define GCSC_GLPCI_GLD_MSR_CAP (GCSC_SB_MSR_BASE + 0x00) 105#define GCSC_GLPCI_GLD_MSR_CONFIG (GCSC_SB_MSR_BASE + 0x01) 106#define GCSC_GLPCI_GLD_MSR_SMI (GCSC_SB_MSR_BASE + 0x02) 107#define GCSC_GLPCI_GLD_MSR_ERROR (GCSC_SB_MSR_BASE + 0x03) 108#define GCSC_GLPCI_GLD_MSR_PM (GCSC_SB_MSR_BASE + 0x04) 109#define GCSC_GLPCI_GLD_MSR_DIAG (GCSC_SB_MSR_BASE + 0x05) 110 111#define GCSC_GLPCI_CTRL (GCSC_SB_MSR_BASE + 0x10) 112#define GCSC_GLPCI_R0 (GCSC_SB_MSR_BASE + 0x20) 113#define GCSC_GLPCI_R1 (GCSC_SB_MSR_BASE + 0x21) 114#define GCSC_GLPCI_R2 (GCSC_SB_MSR_BASE + 0x22) 115#define GCSC_GLPCI_R3 (GCSC_SB_MSR_BASE + 0x23) 116#define GCSC_GLPCI_R4 (GCSC_SB_MSR_BASE + 0x24) 117#define GCSC_GLPCI_R5 (GCSC_SB_MSR_BASE + 0x25) 118#define GCSC_GLPCI_R6 (GCSC_SB_MSR_BASE + 0x26) 119#define GCSC_GLPCI_R7 (GCSC_SB_MSR_BASE + 0x27) 120#define GCSC_GLPCI_R8 (GCSC_SB_MSR_BASE + 0x28) 121#define GCSC_GLPCI_R9 (GCSC_SB_MSR_BASE + 0x29) 122#define GCSC_GLPCI_R10 (GCSC_SB_MSR_BASE + 0x2a) 123#define GCSC_GLPCI_R11 (GCSC_SB_MSR_BASE + 0x2b) 124#define GCSC_GLPCI_R12 (GCSC_SB_MSR_BASE + 0x2c) 125#define GCSC_GLPCI_R13 (GCSC_SB_MSR_BASE + 0x2d) 126#define GCSC_GLPCI_R14 (GCSC_SB_MSR_BASE + 0x2e) 127#define GCSC_GLPCI_R15 (GCSC_SB_MSR_BASE + 0x2f) 128#define GCSC_GLPCI_PCIHEAD_BYTE0_3 (GCSC_SB_MSR_BASE + 0x30) 129#define GCSC_GLPCI_PCIHEAD_BYTE4_7 (GCSC_SB_MSR_BASE + 0x31) 130#define GCSC_GLPCI_PCIHEAD_BYTE8_B (GCSC_SB_MSR_BASE + 0x32) 131#define GCSC_GLPCI_PCIHEAD_BYTEC_F (GCSC_SB_MSR_BASE + 0x33) 132 133/* 134 * AC97 Audio Codec Controller (ACC) 135 */ 136 137#define GCSC_ACC_GLD_MSR_CAP (GCSC_ACC_MSR_BASE + 0x00) 138#define GCSC_ACC_GLD_MSR_CONFIG (GCSC_ACC_MSR_BASE + 0x01) 139#define GCSC_ACC_GLD_MSR_SMI (GCSC_ACC_MSR_BASE + 0x02) 140#define GCSC_ACC_GLD_MSR_ERROR (GCSC_ACC_MSR_BASE + 0x03) 141#define GCSC_ACC_GLD_MSR_PM (GCSC_ACC_MSR_BASE + 0x04) 142#define GCSC_ACC_GLD_MSR_DIAG (GCSC_ACC_MSR_BASE + 0x05) 143 144/* 145 * USB Controller Registers (USB) 146 */ 147 148#define GCSC_USB_GLD_MSR_CAP (GCSC_USB_MSR_BASE + 0x00) 149#define GCSC_USB_GLD_MSR_CONFIG (GCSC_USB_MSR_BASE + 0x01) 150#define GCSC_USB_GLD_MSR_SMI (GCSC_USB_MSR_BASE + 0x02) 151#define GCSC_USB_GLD_MSR_ERROR (GCSC_USB_MSR_BASE + 0x03) 152#define GCSC_USB_GLD_MSR_PM (GCSC_USB_MSR_BASE + 0x04) 153#define GCSC_USB_GLD_MSR_DIAG (GCSC_USB_MSR_BASE + 0x05) 154 155#define GCSC_USB_MSR_OHCB (GCSC_USB_MSR_BASE + 0x08) 156#define GCSC_USB_MSR_EHCB (GCSC_USB_MSR_BASE + 0x09) 157#define GCSC_USB_MSR_UDCB (GCSC_USB_MSR_BASE + 0x0a) 158#define GCSC_USB_MSR_UOCB (GCSC_USB_MSR_BASE + 0x0b) 159 160/* 161 * IDE Controller Registers (IDE) 162 */ 163 164#define GCSC_IDE_GLD_MSR_CAP (GCSC_IDE_MSR_BASE + 0x00) 165#define GCSC_IDE_GLD_MSR_CONFIG (GCSC_IDE_MSR_BASE + 0x01) 166#define GCSC_IDE_GLD_MSR_SMI (GCSC_IDE_MSR_BASE + 0x02) 167#define GCSC_IDE_GLD_MSR_ERROR (GCSC_IDE_MSR_BASE + 0x03) 168#define GCSC_IDE_GLD_MSR_PM (GCSC_IDE_MSR_BASE + 0x04) 169#define GCSC_IDE_GLD_MSR_DIAG (GCSC_IDE_MSR_BASE + 0x05) 170 171#define GCSC_IDE_IO_BAR (GCSC_IDE_MSR_BASE + 0x08) 172#define GCSC_IDE_CFG (GCSC_IDE_MSR_BASE + 0x10) 173#define GCSC_IDE_DTC (GCSC_IDE_MSR_BASE + 0x12) 174#define GCSC_IDE_CAST (GCSC_IDE_MSR_BASE + 0x13) 175#define GCSC_IDE_ETC (GCSC_IDE_MSR_BASE + 0x14) 176#define GCSC_IDE_PM (GCSC_IDE_MSR_BASE + 0x15) 177 178/* 179 * Diverse Integration Logic (DIVIL) 180 */ 181 182#define GCSC_DIVIL_GLD_MSR_CAP (GCSC_DIVIL_MSR_BASE + 0x00) 183#define GCSC_DIVIL_GLD_MSR_CONFIG (GCSC_DIVIL_MSR_BASE + 0x01) 184#define GCSC_DIVIL_GLD_MSR_SMI (GCSC_DIVIL_MSR_BASE + 0x02) 185#define GCSC_DIVIL_GLD_MSR_ERROR (GCSC_DIVIL_MSR_BASE + 0x03) 186#define GCSC_DIVIL_GLD_MSR_PM (GCSC_DIVIL_MSR_BASE + 0x04) 187#define GCSC_DIVIL_GLD_MSR_DIAG (GCSC_DIVIL_MSR_BASE + 0x05) 188 189#define GCSC_DIVIL_LBAR_IRQ (GCSC_DIVIL_MSR_BASE + 0x08) 190#define GCSC_DIVIL_LBAR_KEL (GCSC_DIVIL_MSR_BASE + 0x09) 191#define GCSC_DIVIL_LBAR_SMB (GCSC_DIVIL_MSR_BASE + 0x0b) 192#define GCSC_DIVIL_LBAR_GPIO (GCSC_DIVIL_MSR_BASE + 0x0c) 193#define GCSC_DIVIL_LBAR_MFGPT (GCSC_DIVIL_MSR_BASE + 0x0d) 194#define GCSC_DIVIL_LBAR_ACPI (GCSC_DIVIL_MSR_BASE + 0x0e) 195#define GCSC_DIVIL_LBAR_PMS (GCSC_DIVIL_MSR_BASE + 0x0f) 196#define GCSC_DIVIL_LBAR_FLSH0 (GCSC_DIVIL_MSR_BASE + 0x10) 197#define GCSC_DIVIL_LBAR_FLSH1 (GCSC_DIVIL_MSR_BASE + 0x11) 198#define GCSC_DIVIL_LBAR_FLSH2 (GCSC_DIVIL_MSR_BASE + 0x12) 199#define GCSC_DIVIL_LBAR_FLSH3 (GCSC_DIVIL_MSR_BASE + 0x13) 200#define GCSC_DIVIL_LEG_IO (GCSC_DIVIL_MSR_BASE + 0x14) 201#define GCSC_DIVIL_BALL_OPTS (GCSC_DIVIL_MSR_BASE + 0x15) 202#define GCSC_DIVIL_SOFT_IRQ (GCSC_DIVIL_MSR_BASE + 0x16) 203#define GCSC_DIVIL_SOFT_RESET (GCSC_DIVIL_MSR_BASE + 0x17) 204#define GCSC_NORF_CTL (GCSC_DIVIL_MSR_BASE + 0x18) 205#define GCSC_NORF_T01 (GCSC_DIVIL_MSR_BASE + 0x19) 206#define GCSC_NORF_T23 (GCSC_DIVIL_MSR_BASE + 0x1a) 207#define GCSC_NANDF_DATA (GCSC_DIVIL_MSR_BASE + 0x1b) 208#define GCSC_NANDF_CTL (GCSC_DIVIL_MSR_BASE + 0x1c) 209#define GCSC_NANDF_RSVD (GCSC_DIVIL_MSR_BASE + 0x1d) 210#define GCSC_DIVIL_AC_DMA (GCSC_DIVIL_MSR_BASE + 0x1e) 211#define GCSC_KELX_CTL (GCSC_DIVIL_MSR_BASE + 0x1f) 212#define GCSC_PIC_YSEL_LOW (GCSC_DIVIL_MSR_BASE + 0x20) 213#define GCSC_PIC_YSEL_HIGH (GCSC_DIVIL_MSR_BASE + 0x21) 214#define GCSC_PIC_ZSEL_LOW (GCSC_DIVIL_MSR_BASE + 0x22) 215#define GCSC_PIC_ZSEL_HIGH (GCSC_DIVIL_MSR_BASE + 0x23) 216#define GCSC_PIC_IRQM_PRIM (GCSC_DIVIL_MSR_BASE + 0x24) 217#define GCSC_PIC_IRQM_LPC (GCSC_DIVIL_MSR_BASE + 0x25) 218#define GCSC_PIC_XIRR_STS_LOW (GCSC_DIVIL_MSR_BASE + 0x26) 219#define GCSC_PIC_XIRR_STS_HIGH (GCSC_DIVIL_MSR_BASE + 0x27) 220#define GCSC_MFGPT_IRQ (GCSC_DIVIL_MSR_BASE + 0x28) 221#define GCSC_MFGPT_NR (GCSC_DIVIL_MSR_BASE + 0x29) 222#define GCSC_MFGPT_RSVD (GCSC_DIVIL_MSR_BASE + 0x2a) 223#define GCSC_MFGPT_SETUP (GCSC_DIVIL_MSR_BASE + 0x2b) 224#define GCSC_FLPY_3F2_SHDW (GCSC_DIVIL_MSR_BASE + 0x30) 225#define GCSC_FLPY_3F7_SHDW (GCSC_DIVIL_MSR_BASE + 0x31) 226#define GCSC_FLPY_372_SHDW (GCSC_DIVIL_MSR_BASE + 0x32) 227#define GCSC_FLPY_377_SHDW (GCSC_DIVIL_MSR_BASE + 0x33) 228#define GCSC_PIC_SHDW (GCSC_DIVIL_MSR_BASE + 0x34) 229#define GCSC_PIT_SHDW (GCSC_DIVIL_MSR_BASE + 0x36) 230#define GCSC_PIT_CNTRL (GCSC_DIVIL_MSR_BASE + 0x37) 231#define GCSC_UART1_MOD (GCSC_DIVIL_MSR_BASE + 0x38) 232#define GCSC_UART1_DONG (GCSC_DIVIL_MSR_BASE + 0x39) 233#define GCSC_UART1_CONF (GCSC_DIVIL_MSR_BASE + 0x3a) 234#define GCSC_UART1_RSVD_MSR (GCSC_DIVIL_MSR_BASE + 0x3b) 235#define GCSC_UART2_MOD (GCSC_DIVIL_MSR_BASE + 0x3c) 236#define GCSC_UART2_DONG (GCSC_DIVIL_MSR_BASE + 0x3d) 237#define GCSC_UART2_CONF (GCSC_DIVIL_MSR_BASE + 0x3e) 238#define GCSC_UART2_RSVD_MSR (GCSC_DIVIL_MSR_BASE + 0x3f) 239#define GCSC_DMA_MAP (GCSC_DIVIL_MSR_BASE + 0x40) 240#define GCSC_DMA_SHDW_CH0 (GCSC_DIVIL_MSR_BASE + 0x41) 241#define GCSC_DMA_SHDW_CH1 (GCSC_DIVIL_MSR_BASE + 0x42) 242#define GCSC_DMA_SHDW_CH2 (GCSC_DIVIL_MSR_BASE + 0x43) 243#define GCSC_DMA_SHDW_CH3 (GCSC_DIVIL_MSR_BASE + 0x44) 244#define GCSC_DMA_SHDW_CH4 (GCSC_DIVIL_MSR_BASE + 0x45) 245#define GCSC_DMA_SHDW_CH5 (GCSC_DIVIL_MSR_BASE + 0x46) 246#define GCSC_DMA_SHDW_CH6 (GCSC_DIVIL_MSR_BASE + 0x47) 247#define GCSC_DMA_SHDW_CH7 (GCSC_DIVIL_MSR_BASE + 0x48) 248#define GCSC_DMA_MSK_SHDW (GCSC_DIVIL_MSR_BASE + 0x49) 249#define GCSC_LPC_EADDR (GCSC_DIVIL_MSR_BASE + 0x4c) 250#define GCSC_LPC_ESTAT (GCSC_DIVIL_MSR_BASE + 0x4d) 251#define GCSC_LPC_SIRQ (GCSC_DIVIL_MSR_BASE + 0x4e) 252#define GCSC_LPC_RSVD (GCSC_DIVIL_MSR_BASE + 0x4f) 253#define GCSC_PMC_LTMR (GCSC_DIVIL_MSR_BASE + 0x50) 254#define GCSC_PMC_RSVD (GCSC_DIVIL_MSR_BASE + 0x51) 255#define GCSC_RTC_RAM_LOCK (GCSC_DIVIL_MSR_BASE + 0x54) 256#define GCSC_RTC_DOMA_OFFSET (GCSC_DIVIL_MSR_BASE + 0x55) 257#define GCSC_RTC_MONA_OFFSET (GCSC_DIVIL_MSR_BASE + 0x56) 258#define GCSC_RTC_CEN_OFFSET (GCSC_DIVIL_MSR_BASE + 0x57) 259 260/* 261 * GeodeLink Control Processor (GLCP) 262 */ 263 264#define GCSC_GLCP_GLD_MSR_CAP (GCSC_GLCP_MSR_BASE + 0x00) 265#define GCSC_GLCP_GLD_MSR_CONFIG (GCSC_GLCP_MSR_BASE + 0x01) 266#define GCSC_GLCP_GLD_MSR_SMI (GCSC_GLCP_MSR_BASE + 0x02) 267#define GCSC_GLCP_GLD_MSR_ERROR (GCSC_GLCP_MSR_BASE + 0x03) 268#define GCSC_GLCP_GLD_MSR_PM (GCSC_GLCP_MSR_BASE + 0x04) 269#define GCSC_GLCP_GLD_MSR_DIAG (GCSC_GLCP_MSR_BASE + 0x05) 270 271#define GCSC_GLCP_CLK_DIS_DELAY (GCSC_GLCP_MSR_BASE + 0x08) 272#define GCSC_GLCP_PMCLKDISABLE (GCSC_GLCP_MSR_BASE + 0x09) 273#define GCSC_GLCP_GLB_PM (GCSC_GLCP_MSR_BASE + 0x0b) 274#define GCSC_GLCP_DBGOUT (GCSC_GLCP_MSR_BASE + 0x0c) 275#define GCSC_GLCP_DOWSER (GCSC_GLCP_MSR_BASE + 0x0e) 276#define GCSC_GLCP_CLKOFF (GCSC_GLCP_MSR_BASE + 0x10) 277#define GCSC_GLCP_CLKACTIVE (GCSC_GLCP_MSR_BASE + 0x11) 278#define GCSC_GLCP_CLKDISABLE (GCSC_GLCP_MSR_BASE + 0x12) 279#define GCSC_GLCP_CLK4ACK (GCSC_GLCP_MSR_BASE + 0x13) 280#define GCSC_GLCP_SYS_RST (GCSC_GLCP_MSR_BASE + 0x14) 281#define GCSC_GLCP_DBGCLKCTRL (GCSC_GLCP_MSR_BASE + 0x16) 282#define GCSC_GLCP_CHIP_REV_ID (GCSC_GLCP_MSR_BASE + 0x17) 283 284/* 285 * GPIO registers 286 */ 287 288#define GCSC_GPIOL_OUT_VAL 0x0000 289#define GCSC_GPIOL_OUT_EN 0x0004 290#define GCSC_GPIOL_OUT_OD_EN 0x0008 291#define GCSC_GPIOL_OUT_INVRT_EN 0x000c 292#define GCSC_GPIOL_OUT_AUX1_SEL 0x0010 293#define GCSC_GPIOL_OUT_AUX2_SEL 0x0014 294#define GCSC_GPIOL_PU_EN 0x0018 295#define GCSC_GPIOL_PD_EN 0x001c 296#define GCSC_GPIOL_IN_EN 0x0020 297#define GCSC_GPIOL_IN_INV_EN 0x0024 298#define GCSC_GPIOL_IN_FLTR_EN 0x0028 299#define GCSC_GPIOL_IN_EVNTCNT_EN 0x002c 300#define GCSC_GPIOL_READ_BACK 0x0030 301#define GCSC_GPIOL_IN_AUX1_SEL 0x0034 302#define GCSC_GPIOL_EVNT_EN 0x0038 303#define GCSC_GPIOL_LOCK_EN 0x003c 304#define GCSC_GPIOL_POSEDGE_EN 0x0040 305#define GCSC_GPIOL_NEGEDGE_EN 0x0044 306#define GCSC_GPIOL_POSEDGE_STS 0x0048 307#define GCSC_GPIOL_NEGEDGE_STS 0x004c 308#define GCSC_GPIO_FLTR0_AMNT 0x0050 309#define GCSC_GPIO_FLTR0_CNT 0x0052 310#define GCSC_GPIO_EVNTCNT0 0x0054 311#define GCSC_GPIO_EVNTCNT0_COMP 0x0056 312#define GCSC_GPIO_FLTR1_AMNT 0x0058 313#define GCSC_GPIO_FLTR1_CNT 0x005a 314#define GCSC_GPIO_EVNTCNT1 0x005c 315#define GCSC_GPIO_EVNTCNT1_COMP 0x005e 316#define GCSC_GPIO_FLTR2_AMNT 0x0060 317#define GCSC_GPIO_FLTR2_CNT 0x0062 318#define GCSC_GPIO_EVNTCNT2 0x0064 319#define GCSC_GPIO_EVNTCNT2_COMP 0x0066 320#define GCSC_GPIO_FLTR3_AMNT 0x0068 321#define GCSC_GPIO_FLTR3_CNT 0x006a 322#define GCSC_GPIO_EVNTCNT3 0x006c 323#define GCSC_GPIO_EVNTCNT3_COMP 0x006e 324#define GCSC_GPIO_FLTR4_AMNT 0x0070 325#define GCSC_GPIO_FLTR4_CNT 0x0072 326#define GCSC_GPIO_EVNTCNT4 0x0074 327#define GCSC_GCSC_GPIO_EVNTCNT4_COMP 0x0076 328#define GCSC_GPIO_FLTR5_AMNT 0x0078 329#define GCSC_GPIO_FLTR5_CNT 0x007a 330#define GCSC_GPIO_EVNTCNT5 0x007c 331#define GCSC_GPIO_EVNTCNT5_COMP 0x007e 332#define GCSC_GPIOH_OUT_VAL 0x0080 333#define GCSC_GPIOH_OUT_EN 0x0084 334#define GCSC_GPIOH_OUT_OD_EN 0x0088 335#define GCSC_GPIOH_OUT_INVRT_EN 0x008c 336#define GCSC_GPIOH_OUT_AUX1_SEL 0x0090 337#define GCSC_GPIOH_OUT_AUX2_SEL 0x0094 338#define GCSC_GPIOH_PU_EN 0x0098 339#define GCSC_GPIOH_PD_EN 0x009c 340#define GCSC_GPIOH_IN_EN 0x00a0 341#define GCSC_GPIOH_IN_INV_EN 0x00a4 342#define GCSC_GPIOH_IN_FLTR_EN 0x00a8 343#define GCSC_GPIOH_IN_EVNTCNT_E 0x00ac 344#define GCSC_GPIOH_READ_BACK 0x00b0 345#define GCSC_GPIOH_IN_AUX1_SEL 0x00b4 346#define GCSC_GPIOH_EVNT_EN 0x00b8 347#define GCSC_GPIOH_LOCK_EN 0x00bc 348#define GCSC_GPIOH_POSEDGE_EN 0x00c0 349#define GCSC_GPIOH_NEGEDGE_EN 0x00c4 350#define GCSC_GPIOH_POSEDGE_STS 0x00c8 351#define GCSC_GPIOH_NEGEDGE_STS 0x00cc 352#define GCSC_GPIO_FLTR6_AMNT 0x00d0 353#define GCSC_GPIO_FLTR6_CNT 0x00d2 354#define GCSC_GPIO_EVNTCNT6 0x00d4 355#define GCSC_GPIO_EVNTCNT6_COMP 0x00d6 356#define GCSC_GPIO_FLTR7_AMNT 0x00d8 357#define GCSC_GPIO_FLTR7_CNT 0x00da 358#define GCSC_GPIO_EVNTCNT7 0x00dc 359#define GCSC_GPIO_EVNTCNT7_COMP 0x00de 360#define GCSC_GPIO_MAP_X 0x00e0 361#define GCSC_GPIO_MAP_Y 0x00e4 362#define GCSC_GPIO_MAP_Z 0x00e8 363#define GCSC_GPIO_MAP_W 0x00ec 364#define GCSC_GPIO_FE0_SEL 0x00f0 365#define GCSC_GPIO_FE1_SEL 0x00f1 366#define GCSC_GPIO_FE2_SEL 0x00f2 367#define GCSC_GPIO_FE3_SEL 0x00f3 368#define GCSC_GPIO_FE4_SEL 0x00f4 369#define GCSC_GPIO_FE5_SEL 0x00f5 370#define GCSC_GPIO_FE6_SEL 0x00f6 371#define GCSC_GPIO_FE7_SEL 0x00f7 372#define GCSC_GPIOL_EVNTCNT_DEC 0x00f8 373#define GCSC_GPIOH_EVNTCNT_DEC 0x00fc 374 375#define GCSC_GPIO_ATOMIC_VALUE(pin,feature) \ 376 ((feature) ? \ 377 ((0 << (16 + (pin))) | (1 << (pin))) : \ 378 ((1 << (16 + (pin))) | (0 << (pin)))) 379